TLV 320 POWER TEST TLV 320 15 Sites

TLV 320 POWER TEST

TLV 320 15 Sites • Problem Statement: o Test No 410(VDDA 2/AVDD) is failing drawing higher current. • Stage at issue found: o • Test-Program was converted on the simulator and while debugging on the Tester we found the issue. Current Status : o Root cause to be identified.

• Findings Measured current value at AVDD pin after Reset Pattern is 1. 05 u. A. › The expected current value is between -40 u. A to 40 u. A. o Measured current value at AVDD pin after PWR_2 Pattern is 135 m. A. › The expected current value is between 2. 1 m. A to 3. 2 m. A. o In the Power pattern 7 registers are programmed. We have taken the current readings after each register write to understand which register is causing the higher current. o Tested with 2 devices and two sites. Behavior is same across. o

Current Measurement after individual Registers write Findings • we are measuring high current only after writing data to register 86 and register 93.

Current Measurement after individual Registers write excluding Register 86 and 93

Current Measurements after writing 0000 1001(Data) to Reg 86 and 93 Findings • Writing D 0 bit to 1 of register 86 and 93 causes AVDD to draw High Current.

Current Measurements after writing 0000 1000(Data) to Reg 86 and 93 Findings • If we write D 0 bit to 0 of register 86 and 93, AVDD draws less current.

D 0 bit description

Pattern Description for Power Test

Pattern Description for Power Test