TARLA LLRF Structure mer Faruk Elim TARLA Project

TARLA LLRF Structure Ömer Faruk Elçim TARLA Project Member Ankara University, Institute of Accelerator Technologies

Content Introduction Ø Brief Definiton of μTCA based LLRF Control Systems Ø TARLA System Architecture Ø Software Architecture Ø Current Status and Prospects of TARLA LLRF Control System Ø What is done in TARLA about LLRF System? Ø 28. 02. 2019 ofelcim@tarla. org. tr 2

Introduction The TARLA accelerator is a Free Electron Laser facility producing laser light in a range of 5 -350 um using a 15 -40 Me. V electron beam. q The machine is operated in continues wave (CW) mode and pulsed mode, delivering variable beam currents. q The accelerator is distributed in a normal conducting injector and a superconducting linac fed by solid state power amplifiers. q RF field regulation is performed by a LLRF control system based on the Micro Telecommunication Architecture (MTCA. 4) proposed by DESY. q Aerial View of TARLA LLRF Conceptual Design Report TARLA Layout 28. 02. 2019 ofelcim@tarla. org. tr 3

Brief Definiton of μTCA based LLRF Control Systems State of art superconducting linear accelerators such as TARLA linac require a high quality beam. q To achieve this goal, highprecision acceleration field stability should be maintained by real-time low level radio frequency (LLRF) feedback control systems. q Syste m TARLA Electron Beam Parameters 260 Amplitude 0. 5 [%] MHz Bunch Phase 0. 2 er [deg] 1. 3 Amplitude 0. 1 [%] GHz Bunch Phase 0. 1 er [deg] Amplitude 0. 1 1. 3 [%] GHz Phase S. C. 0. 1 [deg] 0. 2 0. 8 0. 5 0. 15 0. 8 0. 2 0. 08 0. 5 0. 2 0. 08 0. 25 0. 1 0. 05 0. 25 0. 1 0. 04 0. 25 0. 1 LLRF regulation performance, estimation based on measurement results from comparable systems being operated with the same setup. TARLA LLRF Conceptual Design Report 28. 02. 2019 Value Jitter Drift Grante Expect d ed ofelcim@tarla. org. tr 4

Brief Definiton of μTCA based LLRF Control Systems Micro. TCA is an open standard embedded computing system. q It has rear I/O and multichannel A/D and D/A conversion boards. q It is also fed from FPGA’s gate level digital computing speed. q https: //schroff. nvent. com/en/schroff-na/MTCA 28. 02. 2019 ofelcim@tarla. org. tr 5

Brief Definiton of μTCA based LLRF Control Systems After being filtered by digital The IF signals are sampled in the The combined signals are fed The I/Q signals are fed to a Then, the I/Q errors are Figure shows the block next stage and fed to a μTCA to the I/Q modulator by a rotation matrix to low-pass filters, the I/Q regulated by a proportional diagram of a typical LLRF FPGA to execute the DSP digital to analog converter compensate the loop phase. components are compared and integral (PI) FB controller. system. The RF pick-up algorithms. The baseband in the (DAC) to modulate the RF The vector-sum signal is then with the set values and the The regulated I/Q signals are signals from all the cavities phase and quadrature signal from the master obtained by calculating the I/Q errors are calculated. added to the feedforward are down-converted to components (I/Q) are extracted oscillator. Finally, the LLRF FB superposition of all the cavity (FF) models. intermediate frequency (IF) from the IF signal by digital IQ loop is closed by means of a pick-up signals. detection algorithm. highpower source, which drives the cavities. 28. 02. 2019 ofelcim@tarla. org. tr F. Qiu et al. , Development of Micro. TCA-Based Low-level Radio Frequency Control Systems for c. ERL and STF, Oct 2018 6

TARLA LLRF System Architecture Following the beam Additionally all SC Finally the beam passes The sub-harmonic In the next stage a so downstream the next The RF control in cavities are equipped buncher cavity is the first two cryomodule (CM), cavity passed is the cavity seen by the called macro-pulser with a set of TARLA handles the each housing two fundamental buncher. electron beam, after it’s superconducting Tesla piezoelectric tuners, captures unwanted sub-harmonic and generated by the This device operates at type 1. 3 GHz cavities. In which are used to thermionic electron gun. electron bunches and 1. 3 GHz and in charge of fundamental buncher between both CM a The principle of this maintain the reducing the bunch transmits the as well as the 4 bunch compressor is bunching state is velocity resonance frequency length further down to 10 installed which further bunching. Beside the electron bunches superconducting of the cavities in ps, which is still be done other RF systems running reduces the bunch length. which are used for by velocity bunching, e. g. presents of cavities housed in at 1. 3 GHz, this cavity Each cavity is supplied by the tail of the bunch is operates on 260 MHz at a disturbances like the FEL. two cryomodules. a 16 k. W solid state maximum input power of accelerated, the head mechanical vibration amplifier (SSPA). 1 k. W. decelerated. of the system. TARLA LLRF Conceptual Design Report 28. 02. 2019 ofelcim@tarla. org. tr 7

Software Architecture Each Digitizer(RTM) and Then Chimera. TK based server takes these registers AMC board that is as input and/or output and connected to MTCA crate creates logical algorithm. have dedicated address Each algorithm has necessary space containing various properties that are transparent to the higher registers responsible from level. Server then exposes its one specific property of properties via Control the board or the System Adapter to EPICS, application part. These giving higher level user registers are connected to interface to have slow control and monitoring higher level via PCIe capabilities over the server. protocol. ity F Cav ng R t s r Fi Usi h from LA Site by p a r g Photo ion in TAR F System R at Oper 4 based LL. MTCA The general overview of software connection from the highest level (User Interface) to the lowest level (register level) TARLA LLRF Conceptual Design Report 28. 02. 2019 ofelcim@tarla. org. tr 8

Current Status and Prospects of TARLA LLRF Control System MTCA. 4 is developed and used in the DESY Micro. TCA Lab and as the LLRF control system for the European XFEL experiments. Integration and development of TARLA LLRF system is taking place at DESY. In order to build up the system in collaboration between DESY and TARLA the following tasks are going to be fulfilled. q q Development and delivery of supporting system components System integration and test of Hardware, Firmware and Software q System commissioning on TARLA site q Training of TARLA staff to operate the system q Final report and performance measurements TARLA LLRF Cabinet in DESY Site Front View 28. 02. 2019 ofelcim@tarla. org. tr TARLA LLRF Cabinet in DESY Site Rear View 9

What is done in TARLA about LLRF System? TARLA has an additional MTCA. 4 crate for research and development purpose. In current status we are able to operate one of the N. C. cavity and one of Cryomodule that includes 2 S. C. cavity. S. Henderson, SPAFOA, June 20, 2012 http: //www. accelerators-for-society. org/ 28. 02. 2019 TARLA LLRF and R&D Spare Crate Front View ofelcim@tarla. org. tr TARLA LLRF and R&D Spare Crate Rear View 10

What is done in TARLA about LLRF System? – Interlock Converter LLRF system of TARLA running on MTCA. 4 and it gives status information as LVDS (Low Voltage Differential Signaling) and takes interlock as 3. 3 VDC in failsafe mode. For this reason, to achive communication between MPS(Machine Protection System) and LLRF crate there should be a converter for both directions. LLRF Interlock Converter device designed, manufactured and tested by TARLA to match the MPS with the available LLRF interlock functionalities. Layout of TARLA LLRF Interlock Distrubition 28. 02. 2019 ofelcim@tarla. org. tr 11

What is done in TARLA about LLRF System? – Interlock Converter q “LLRF Interlock Converter Device” is located between MPS and LLRF Crate. q And the device includes some ICs and isolator components and some connectors. q Therefore, it was expected to cause a delay in signals passing through the device. q This delay should be measured before operation. q So following setup is prepared. TARLA LLRF Interlock Converter Device 28. 02. 2019 ofelcim@tarla. org. tr Delay Measurement Setup for LLRF Interlock Converter Device 12

What is done in TARLA about LLRF System? – Interlock Converter As seen in figures, 5µs delay occures after status changing of MTCA. 4. And 30µs delay occures after interlock reaction of MPS. These delays are highly acceptable for TARLA Interlock System. 28. 02. 2019 Status Changing on MTCA. 4(yellow) and LLRF Interlock Converter Device reaction to MPS (blue) Interlock Signal from MPS(yellow) and LLRF Interlock Converter Device reaction to LLRF Crate(blue) ofelcim@tarla. org. tr 13

What is done in TARLA about LLRF System? – LOGM RMS Jitter Measurements The Local Oscillator Generation Module (LOGM) receives the 1. 3 GHz reference signal from M. O. (Master Oscillator), internally divides and mixes the RF signal to produce a 1354 MHz local oscillator signal (LO) used by the RTM down-converters. The 65 MHz external clock (CLK) signal is also generated for the digitizers. For RF reference tracking, the 1. 3 GHz signal is split and distributed to one channel of each MTCA. 4 RTM down-converter module. 28. 02. 2019 The Local Oscillator Generation Module (LOGM) ofelcim@tarla. org. tr 14

What is done in TARLA about LLRF System? – LOGM RMS Jitter Measurements The RMS jitter values of the output signals of the LOGM device to be used in the LLRF system are important for LLRF stability. For this reason, RMS jitter measurements of this device were made. Since the signal output levels of the MO device are below 21 d. Bm, which is the minimum input value of the LOGM Signal Generator RMS Jitter Measurement Setup device, a 30 d. Bm signal generator is used. 28. 02. 2019 ofelcim@tarla. org. tr LOGM RMS Jitter Measurement Setup 15

What is done in TARLA about LLRF System? – LOGM RMS Jitter Measurements Considering that the LOGM device has 36 signal outputs, the RMS jitter measurement results of the signal generator and one of the signal outputs used for measurement are shown. As seen in figures, when the RMS jitter value from the signal generator is subtracted from the output values, The 60 Hz - 10 MHz integrated additive jitter for the LO is about 2 fs RMS as expected. Signal Generator RMS Jitter Measurement Result One of the LOGM Outputs RMS Jitter Measurement Result 28. 02. 2019 ofelcim@tarla. org. tr 16

Acknowledgemenets q This study is supported by Presidency Strategy and Budget Directorate under grant number 2006 K 120470. 28. 02. 2019 ofelcim@tarla. org. tr 17

Thank You for Your Attention 28. 02. 2019 ofelcim@tarla. org. tr TARLA Team 18