SRP Architecture Irakli MANDJAVIDZE DAPNIA CEA Saclay 91191
- Slides: 6
SRP: Architecture Irakli MANDJAVIDZE DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette, France Irakli. MANDJAVIDZE@cea. fr ODE Workshop, LIP, 07 -08/04/05
Overview l l SRP in ECAL Off-Detector Electronics The Selective Read-out Processor The SRP architecture The Algorithm Board Irakli. MANDJAVIDZE@cea. fr ODE Workshop, LIP, 07 -08/04/05 2
SRP in ECAL OFF-Detector Electronics Partial trigger primitives Front-ends 108 TCC Trigger Towers L 1 Trigger L 1 accept 54 DCC All event data Classification flags: 3 bit/TT Input pipeline delay of 6. 4µs/RU Read-out flags: 3 bit/TT Selected event data HLT & DAQ Irakli. MANDJAVIDZE@cea. fr SRP 12 algorithm boards 54 CCS TTC s. TTS l Operation → Receive TT flags from TCCs → Exchange frontier TT flags among ABs → Execute SR algorithm → Deliver SR flags to DCCs ODE Workshop, LIP, 07 -08/04/05 3
The Selective Read-out Processor l Architecture → A 6 U VME 64 x crate → 12 identical Algorithm Boards l Interfaces → Optical serial links for: 1 -slot VME 64 x compliant four ECAL partitions → Crate controller → Boundary scan controller (? ) TCC-AB and AB-DCC AB-AB → A TTC interface per AB → A TTS interface per partition s. TTS signals of 3 ABs merged. . . and sent by any of the ABs l Operation → Receive TT flags from 108 TCCs from up to 12 TTCs per AB → Exchange frontier TT flags among ABs among up to 8 ABs → Execute SR algorithm → Deliver SR flags to 54 DCCs to up to 6 DCCs per AB Irakli. MANDJAVIDZE@cea. fr ODE Workshop, LIP, 07 -08/04/05 4
SRP Architecture Parallel optic modules l Algorithm Board → under development → 2 boards expected in September l SRP crate Left end-cap Left ½ barrel Right ½ barrel end-cap Rx: TCC input Tx: DCC output C B A A A C S B B B Rx: AB input Four Partitions Tx: AB output RJ 45 TTC input TTS input 1 TTS input 2 TTS output Irakli. MANDJAVIDZE@cea. fr ODE Workshop, LIP, 07 -08/04/05 5
Algorithm Board P 1 J 0 VME buffers Core FPGA Memory SNAP 12 MSA pluggable parallel optic modules T T C Rx D C C Tx Power supply Xilinx V 2 Pro xc 2 vp 70 -6 -ff 1704 BS controller & JTAG chain FPROMs P 2 A B Rx Tx VME Serial links Algorithms Clock synthesizer TCS interface QPLL TTCrx RJ 45 connectors True. Lite Aux. connector Cons. , JTAG TTS TTS O/E Ethernet IN IN OUT Same hardware for AB and AB Tester Irakli. MANDJAVIDZE@cea. fr ODE Workshop, LIP, 07 -08/04/05 6
