Interrupt Driven IO on the Mano CPU Doing

Interrupt Driven I/O on the Mano CPU Doing things decently and in order

Final Phase of Instruction Cycle Simulation l l FETCH DECODE EXECUTE CHECK FOR INTERRUPTS (CFI)

I/O Device Issues l l Devices operate asynchronously with respect to the CPU Devices operate slowly with respect to the CPU Devices must request service Devices must hold pending requests

Alternative I/O Approaches l Polling – – – l Cycle through I/O devices Process as needed Polling consumes CPU cycles Interrupts – – Adds hardware complexity (IEN, FGI, FGO, TR, OUTR, INPR) Complicates CU design (especially for pipelined CPUs)

Semantics for CFI l Conditions for CFI: T 0’ T 1’ T 2’ IEN (FGI+FGO) – – l T 0’, T 1’, T 2’: Not during FETCH or DECODE (or EXECUTE!) IEN: interrupts must be enabled FGI or FGO: a device requests service If T 0’ T 1’ T 2’ IEN (FGI+FGO), then R<-1 Actions required to switch to interrupt handler (What to do if R equals 1. ) – – – RT 0: AR<-0, TR<-PC RT 1: M[AR]<-TR, PC<-0 RT 2: PC<-PC+1, IEN<-0, R<-0

Testing CFI l l Use an I/O script Script entries contain (see the assignment) – – l l Request time Input register values Tests will only assess input operations Conditions the device simulator implements – – Time. CC ≥ Time[ next. Request ] FGI = 0

Processing Steps For Simulating Input Device Service Requests l Conditions – – – l There is a request for service Time has advanced to the scripted request Any previous input service request has acquired a value from the INPR and cleared FGI = 0. Actions – – – Copy the value into the INPR Set FGI=1 Advance the script cursor (to the next request)

A Problem l What must happen before returning from the Interrupt Service Routine (ISR)? – l How does control return from a subroutine? – l IEN<-1 via the ION instruction BUN I ZRO Suppose a request for service is pending when ION is executed in the ISR – IEN and FGI are 1 => CFI transfers to ISR with a return to the BUN I !!!!!!!!!!!!!!!!!!!!!

Final Simulator Demonstration l ADD an RTI instruction to the simulator – – – l l RTI has hexadecimal representation F 020 Uses 2 clock cycles to execute Semantics: AR<-0, IEN<-1; PC<-M[AR] Use the script from the assignment Apply to CPUTest 13. dat and CPUTest 14. dat – – CPUTest 13. dat produces an infinite loop CPUTest 14. dat executes in exactly 457 clock cycles