HCC Derived Clocks Generated Clocks The HCC generates

HCC Derived Clocks

Generated Clocks The HCC generates two clocks from the e. PLL 160 MHz clocks and the chip 40 MHz clock, used as a reference: An 80 MHz clock using a divide by 2 circuit that contains no loops and so is self clearing. A 40 MHz clock that should be less sensitive to perturbations in the GBT supplied clock. 40 April 2014 HCC Derived Clocks 2

div 2 Circuit Positive and Negative edges of 40 MHz clock produce pulses into second DFF. These are sampled at 160 MHz. Simulations show circuit working for most phases between 40 and 160 MHz clocks (~200 ps out of 6. 25 ns fail) and for 50/50, 25/75, 75/25 duty cycle on 40 MHz. 40 April 2014 HCC Derived Clocks 3

div 4 Circuit • Circuit samples reference 40 MHz clock at 160 MHz into a 4 -bit shift register. • 40 MHz clock is generated by separate 4 -bit shift register at 160 MHz – clk[3: 0] <= {clk[2: 0], ~clk[1]}; 40 April 2014 HCC Derived Clocks 4

div 4 Local Reset • Set by external reset • Set by 4 mismatches between reference and generated 40 MHz sampled shift registers • Loads reference 40 MHz shift register into generated 40 MHz shift register • Count of local resets made available in a register 40 April 2014 HCC Derived Clocks 5

div 4 simulation Extra pulse 3. 25 ns phase Error count 40 April 2014 HCC Derived Clocks 3. 25 ns phase Local Reset Pulse 6

div 4 Simulation (2) Long Pulse 40 April 2014 HCC Derived Clocks 7

div 4 To Do • Understand reasonable failure modes on 40 MHz from GBT • Simulate with e. Pll response included • Explore phasing between ref 40 MHz and 160 MHz • Are there failure modes of this approach? 40 April 2014 HCC Derived Clocks 8