Graphics on GPU David KirkNVIDIA and Wenmei W

Graphics Pipeline • Process objects one at a time in the order they are

Texture Mapping Example Texture mapping example: painting a world map texture image onto a

Open. GL Architecture geometry pipeline Immediate Mode Polynomial Evaluator CPU Display List Per Vertex

CPU Host Interface Vertex Control VS/T&L GPU Vertex Cache A Fixed Function GPU Pipeline

Programmable Vertex and Pixel Processors 3 D Application or Game 3 D API Commands

Unified Graphics Pipeline Host Data Assembler Setup / Rstr / ZCull SP SP SP

CPU "Host" main() Id: 1 2 x Points: y z Colours: . . .

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Graphics on GPU © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 -2010 ECE 408, University of Illinois, Urbana-Champaign 1

Graphics Pipeline • Process objects one at a time in the order they are generated by the application – Can consider only local lighting • Pipeline architecture display • All steps can be implemented in hardware on the graphics card 2 E. Angel and D. Shreiner: Interactive

Texture Mapping Example Texture mapping example: painting a world map texture image onto a globe object. © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 -2010 ECE 408, University of Illinois, Urbana-Champaign 3

Open. GL Architecture geometry pipeline Immediate Mode Polynomial Evaluator CPU Display List Per Vertex Operations & Primitive Assembly Rasterization Per Fragment Operations Frame Buffer Texture Memory 4 Pixel Operations Angel: Interactive Computer Graphics 5 E

CPU Host Interface Vertex Control VS/T&L GPU Vertex Cache A Fixed Function GPU Pipeline Triangle Setup Raster Shader Texture Cache ROP © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 -2010 FBI ECE 408, University of Illinois, Urbana-Champaign Frame Buffer Memory 5

Programmable Vertex and Pixel Processors 3 D Application or Game 3 D API Commands CPU 3 D API: Open. GL or Direct 3 D CPU – GPU Boundary GPU Command & Data Stream GPU Front End Assembled Polygons, Lines, and Points Vertex Index Stream Primitive Assembly Pre-transformed Vertices Pixel Location Stream GPU Rasterization & Interpolation Rasterized Transformed Pre-transformed Vertices Fragments Programmable Vertex Processor Pixel Updates Raster Operation s Framebuffer Transformed Fragments Programmable Fragment Processor An example of separate vertex processor and fragment processor in a programmable graphics pipeline © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 -2010 ECE 408, University of Illinois, Urbana-Champaign 6

Unified Graphics Pipeline Host Data Assembler Setup / Rstr / ZCull SP SP SP TF L 1 SP SP Pixel Thread Issue SP TF © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007 -2010 ECE 408, University of Illinois, Urbana-Champaign SP SP TF L 1 L 2 FB SP SP TF L 1 L 2 FB SP Geom Thread Issue SP TF L 1 L 2 FB SP L 1 L 2 FB Thread Processor Vtx Thread Issue L 2 FB 7

CPU "Host" main() Id: 1 2 x Points: y z Colours: . . . Memoy(data): GPU . . . x y z . . . r r g g b b . . . H. W CPU Code Vertex shader Pixel shader Identified table Id Name 1 Vsource 2 Vobj 3 Vposition 4 Vcolour 5 Psource © David Kirk/NVIDIA and Wen-mei W. Hwu, 6 2007 -2010 Pobj ECE 408, University of Illinois, Urbana-Champaign Location main(). . . 1010. . . . 8