Versatile Link FPGAbased BitErrorRatio Tester for SEUhardened Optical

Versatile Link FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links Csaba SOOS, Stéphane DETRAZ, Sérgio SILVA, Paulo MOREIRA, Spyridon PAPADOPOULOS, Ioannis PAPAKONSTANTINOU, Christophe SIGAUD, Pavel STEJSKAL, Jan TROSKA CERN, PH-ESE

Introduction Versatile Link ● Stringent requirements ● High speed, low power, high reliability, long lifetime etc. ● Harsh environment ● Noise, radiation etc. ● The answer: Versatile Link and GBT projects Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 2

Challenges (1/2) Versatile Link ● Amplitude noise ● Low-swing signals => reduced SNR ● Phase noise, i. e. Jitter ● Reduced bit period => less tolerance Receiver electrical signal Csaba Soos et al. Receiver electrical signal, when the optical signal is attenuated TWEPP '09, 21 -25 September, 2009 3

Challenges (2/2) Versatile Link ● Radiation effects ● Single-Event Upsets in the photodiode and in the receiver subassembly ● In the SEU dominated region, the BER is almost independent from the SNR Jan Troska et al. , “Single-Event Upsets in Photodiodes for Multi-Gb/s Data Transmission”, TWEPP 2008, Naxos, Greece Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 4

Test methods ● Eye diagram ● Good qualitative measurement ● Difficult to predict the bit error rate ● Used for mask tests (standards) Csaba Soos et al. Versatile Link ● Bathtub curve ● Links the jitter performance to the bit error rate ● Ignores the amplitude noise ● Not precise at low bit error rate (extrapolation) TWEPP '09, 21 -25 September, 2009 5

Bit Error Rate testing Versatile Link ● Simple method for evaluating the performance of the entire transmission channel ● The measurement time depends on the required confidence level and the number of errors observed T BER R CL n N Csaba Soos et al. – measurement time – target bit error rate – data rate – confidence level – number of transmitted bits – number of error bits TWEPP '09, 21 -25 September, 2009 6

Motivations to build a custom BERT Versatile Link ● Limitations of the oscilloscope ● Sampling rate, memory, extrapolation, long measurement time ● We would like to use custom physical layer protocol (GBT) ● It will allow us to study the performance of the protocol ● Standard BERT uses pseudo-random bit pattern ● We would like to carry out tests on multiple channels ● It will reduce the overall test time ● Standard BERT can typically handle one channel at a time ● Error logging ● Required for off-line analysis ● Limited in standard BERT equipments Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 7

BERT system architecture Versatile Link External memory On-chip memory UART RS 232 PLB 0 PPC 440 On-chip memory Crossbar PLB 1 BERT core GBT DUT So. C implemented on the ML 523 Virtex 5 transceiver evaluation platform Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 8

Bit Error Tester – Single Channel Generator Error inject GBT Encoder MGT TX Compare Line errors Compare System errors Csaba Soos et al. GBT Decoder GBT core TWEPP '09, 21 -25 September, 2009 High-speed Serial 4. 8 Gbit/s Control Versatile Link DUT MGT RX Hard IP 9

Development platform Versatile Link ML 523 Virtex 5 transceiver evaluation platform featuring: XC 5 VFX 100 T device - 8 GTX dual tiles - 16, 000 slices - 256 DSP 48 E blocks - 8, 208, 000 bits internal memory + 128 MB DDR 2 external memory Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 10

Test system J-BERT N 4903 A Versatile Link Clock source Attenuator BERT electrical optical Agilent Power meter 8163 B + 81635 A Labview Csaba Soos et al. Agilent 8156 A TWEPP '09, 21 -25 September, 2009 11

Graphical user interface - Labview Measurement settings Stop criteria Versatile Link Result plots Log file path Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 12

Measurement flowchart Versatile Link start Initialize ● To improve speed, measurements are started from the highest attenuation value ● If a channel cannot acquire lock, it will be masked ● Stop criteria: target BER, confidence factor, time ● Record values: BER bounds, confidence factor, time, average optical power ● The loop is finished, when we reach the target BER on all channels Set attenuation N Locked ? Y Read counters Stop criteria ? Y Write log N End loop ? Y Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 N end 13

Results – System and Line BER Control Error inject GBT Encoder MGT TX High-speed Serial 4. 8 Gbit/s Generator Compare Line errors Compare System errors Csaba Soos et al. Versatile Link GBT Decoder GBT core TWEPP '09, 21 -25 September, 2009 DUT MGT RX Hard IP 14

Results – Scope vs. BERT Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 Versatile Link 15

Future work Versatile Link ● Optimize the system for multi-channel readout ● FPGA resource usage (clock network and PLLs) ● Labview script ● Implement advanced logging ● Record erroneous words with timestamp ● Add support for multiple line rates ● Dynamic reconfiguration of the multi-gigabit transceivers ● Prepare the system for the SEU tests ● Test components in radiation Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 16

Conclusion Versatile Link ● Future, radiation-hard optical links will have to meet strict requirements ● The physical layer protocol will have to deal with the radiation induced errors (GBT) ● Bit-Error-Rate testing can be used to characterize the link components quantitatively ● Advanced testing (error logging) can provide insights into how error propagates in the system ● FPGA-based BERT system supporting the above mentioned features has been developed ● Link components are being tested in the lab, and will be tested soon (November 2009) in radiation Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 17

Versatile Link Thank You ! Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 18

System architecture – Virtex 4 JTAG Debug On-chip memory PPC 405 GBT Bit Error Rate Tester Versatile Link RS 232 UART BERT core GBT DUT PLB Csaba Soos et al. TWEPP '09, 21 -25 September, 2009 19