Verilog A Overview The schematic of the Verilog

Verilog. A Overview § The schematic of the Verilog. A transistor model is shown here. It is a table lookup-based model. The tables for Id. Vg, Cgd and Cgs are obtained using the TCAD models § The TCAD models are the same as those shown in the previous except that the gate lengths are all set to LG 20 nm § The parasitic Series Resistance and parasitic External Capacitance are not included in the TCAD model and are to be added at the circuit level as shown in the schematic above

Assumption for TFET Verilog. A Models § For the Tunnel FETs, we assume identical drive-currents for the n-channel and pchannel transistors § The electron and hole Density-of-States can be quite different in III-Vs. We assume different Gate capacitances for the n-type and p-type transistors § For Si MOSFETs, we assume identical drive-currents and gate capacitances for n-type and p-type transistors

Spectre Circuit Simulation § In order to execute the circuit simulations you need to have Virtuoso Spectre Circuit Simulator installed § In order to run the idvg simulation use: spectre In. As_ntfet_idvg. scs § In order to run the FO 1 inverter simulation use: § spectremdl –b inverter_In. As_tfet_FO 1. mdl –d inverter_In. As_tfet_FO 1. scs –measure inverter_In. As_tfet_FO 1. measure § In order to run the Ring Oscillator simulation use § spectremdl -b In. As_Ring_Oscillator. mdl -d In. As_Ring_Oscillator. scs – measure In. As_Ring_Oscillator. measure