Ultralow Power for Alwayson with Minima Dynamic Margining

Lowering Voltage and Energy in Real Time 101 Quadratic Energy Savings Higher energy Run

UP TO 15 x Ultra-Wide DVFS required Higher energy Energy Loss BLE L 2

With E= CV 2, Much Left on the Table 10 9 8 UP TO

Real-World Measurement Examples SHA 256, Commercial DSP IP • Keyword spotting: 2, 6 x

Solution: Margin Dynamically Conventional Design CLK Process Minima Margining Pre-Silicon Voltage Temperature CLK Feedback

Create Feedback Loop with In-Situ Monitors Detections CLK control

Several Feedback Loops Required HW Minima clock architecture HW Minima PM s of n

Loops in Dynamic Margining BTLE Stack @ 0. 7 V, 64 MHz, SS chip

2 nd-Order Benefits: Power Distribution SS limits speed Reduced power variation! FF sets the

Minima: The Product Minima API analyzes your code for optimal energy states Application Code

Final Thoughts • Radio energy: 100 n. J/bit (Zigbee), 50. 00 n. J/bit (BLE),

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Ultra-low Power for Always-on with Minima Dynamic Margining Lauri Koskinen, CTO, Minima Processor

Lowering Voltage and Energy in Real Time 101 Quadratic Energy Savings Higher energy Run to Completion Just-in-Time DVFS Higher voltage Near-Threshold Operation Time Task DL

UP TO 15 x Ultra-Wide DVFS required Higher energy Energy Loss BLE L 2 CAP BLE LINK Detection AUDIO No detection Higher voltage Legacy µC, 1 -2 VDDs, CLK scaling AUDIO AI

With E= CV 2, Much Left on the Table 10 9 8 UP TO 15 x 7 Audio BTLE Crypto Video WIFI GPS High perf 6 5 4 3 2 1 0 Energy savings Conventional technology

Real-World Measurement Examples SHA 256, Commercial DSP IP • Keyword spotting: 2, 6 x energy savings • ARM KWS reference SW split into two tasks: 3, 5 x Energy Savings • Speech-band energy detection (20 MHz / ARM M 3) • CNN (200 MHz / ARM M 3) • Higher energy saving with lowactivity data (silent room) • Operation point change overhead: • 250 cycles (SW) + 550 cycles (DCDC 15 m. V/µs)

The Challenge Margins

Solution: Margin Dynamically Conventional Design CLK Process Minima Margining Pre-Silicon Voltage Temperature CLK Feedback loop delay, Gate functionality, etc. Minima CLK Margining Working Silicon With DVFS intermittent large margin averages => 0

Create Feedback Loop with In-Situ Monitors Detections CLK control

Several Feedback Loops Required HW Minima clock architecture HW Minima PM s of n s n e T SW OS governors, Power profiles, Minima drivers

Loops in Dynamic Margining BTLE Stack @ 0. 7 V, 64 MHz, SS chip Housekeeping @ 0. 4 V, 2 MHz, SS chip Minima HW – SW Interface Housekeeping @ 0. 35 V, 2 MHz, SS chip

1 st Feedback Loop Measurements 1

2 nd-Order Benefits: Power Distribution SS limits speed Reduced power variation! FF sets the high power point (and leakage) UW-DVFS Power Spread Up To 2 x

Minima: The Product Minima API analyzes your code for optimal energy states Application Code RTOS DVFS Drivers Ultra-Wide DVFS HW enabled by Minima soft IP Easily integrable driver offers constant performance or energy minimization per application or data Minima technology integrable to any IP: ARM, RISC-V, DSP

Final Thoughts • Radio energy: 100 n. J/bit (Zigbee), 50. 00 n. J/bit (BLE), 3. 70 n. J/bit (Wifi) • Memory energy: ~100 p. J • Local memory accesses, DRAM accesses • Flash much more • Processor energy today: ≥~50 pj • (CMOS) Processor minimum energy ~5 pj • Memory compression becomes cheaper in terms of energy • Edge computing (contextual computing, fog computing, etc. ) becomes cheaper in terms of energy Acknowledgements Ali M. Niknejad

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