TELL 40 VELO time ordering Pablo Vzquez Jan
TELL 40 VELO time ordering Pablo Vázquez, Jan Buytaert, Karol Hennessy, Marco Gersabeck, Pablo Rodríguez 12/12/2013 P. Vazquez (U. Santiago) 1
Time ordering • Packet(34 b)=ASIC(4 b)+Superpixel. Address(13 b)+BCID(9 b)+Hitpattern(8 b) • Data packets arrive to the TELL 40 disordered in time • Time ordering = grouping of packets by 9 bit BCID value • Grouping is done in 2 steps: – Router based on 4 -bits of BCID (MSB or LSB, see later) – Memory storage remaining 5 -bits BCID his talk Goal of t “VELO” “Standard LHCb” Decoding routing memory Data processing 12/12/2013 P. Vazquez (U. Santiago) 2
4 -bit BCID VELO packet router • Non blocking scheme using internal memory (FIFO’s) • Different number of input links considered: – 16 @160 MHz (320) for a half (full) module as described in the TDR – 10 @320 MHz for a full module, when reducing optical links • 2 architectures under study: – “Cascade” of 1 -bit router elements. Each element routes packets based on 1 -bit – “crossbar” : single stage N x 2 M ports routes packets based on all bits • Use of altera library megafunctions: lpm_scfifo, lpm_compare. . . 12/12/2013 P. Vazquez (U. Santiago) 3
1 -bit router elements w 0 If (BID[i]=0) Write FIFO_00 else Write FIFO_01 Data 0 w 1 If (BID[i]=0) Write FIFO_10 else Write FIFO_11 Data 1 FIFO_00 r 0 More Full? MUX 2 -to-1 FLIP FLOP Out 0 FIFO_01 FIFO_10 r 1 More Full? MUX 2 -to-1 FLIP FLOP Out 1 FIFO_11 r 0 w 0 Data 0 If (BID[i]=0) Write Flip. Flop 0 else Write Flip. Flop 1 Flip. Flop 0 Out 0 r 1 Flip. Flop 1 Out 1 2 x 2 router element uses 4 fifos while 1 x 1 router element doesn’t use fifos 12/12/2013 P. Vazquez (U. Santiago) 4
10 x 16 router with “ 1 -bit router elements” 0000 2 x 2 port 1 -bit router xxxx 0 xxxx 1 12/12/2013 1 x 2 port 1 -bit router xx 01 xx 11 P. Vazquez (U. Santiago) 1111 5
FPGA resources and max speed • Several configurations compiled for the actual device: altera stratix V 5 SGXEA 7 N 3 F 45 C 2 • Router can run @ 320 MHz with 1 -5% of resources with a cross-sectional bandwidth 1. 6 -2. 6 higher than required (2 G pakets/s peak for full module) In x Out links 16 x 16 (TDR) 10 x 16 (Optimized) Fifo depth (words) 512 Logic utilization (in ALMs) 3, 582 ( 2 % ) 2, 722 ( 1 % ) Total registers 3839 4305 Total block memory bits 58, 920 ( < 1 % ) 1, 274, 940 ( 2% ) M 20 K blocks 128 ( 5 % ) 84 ( 3 % ) Fmax 85ºC (MHz) 340 361 Bandwidth links x 320 MHz (G packet/s) 5. 12 3. 2 12/12/2013 P. Vazquez (U. Santiago) 6
Simulation • Generate simulated input data using the known distribution of the event size and latency (see next slides) • Aim: the dependency of packet loss vs fifo depth and routing strategy (MSB vs LSB bits) – Aim: data packet loss << 0. 1%? • Every 34 -bit FIFO is allocated on a M 20 K memory block => optimal is 512 x 40 bit. Could be extended • We will start simulating the 10 x 16 @320 MHz case 12/12/2013 P. Vazquez (U. Santiago) 7
Event size distribution • The 20 inputs of a full module are below 40% of peak packet rate capacity At the input of router @320 MHz Links 1 -8 Links 9 -12 Link 13, 14 Link 15, 16 Link 17, 18 Link 19, 20 mean 0. 37 pkt/clk mean 0. 31 pkt/clk mean 0. 25 pkt/clk mean 0. 30 pkt/clk mean 0. 26 pkt/clk mean 0. 16 pkt/clk eu B an m ro f a om k ze v in t r Ma t Da 12/12/2013 P. Vazquez (U. Santiago) 8
Simulation latency • Packets arrive at the tell 40 with variable latency: probability • Routing with the MSB bits generates data rate peaks 10 times higher than routing with LSB bits – increases packet loss probability (but maybe still acceptable), – but is nicer for MEP: consecutive events are stored in the same memory – Maybe better suited for dataprocessing (idle time between peaks) 12/12/2013 P. Vazquez (U. Santiago) 9
Summary • TELL 40 VELO router block has been investigated • Compilation of designs based on 1 -bit router elements shows that with 1 -5% of FPGA resources, the router can handle easily the required bandwidth • Simulations with self-generated data will show the packet loss (with respect to fifo depth and MSB/LSB routing strategy) 12/12/2013 P. Vazquez (U. Santiago) 10
backup 12/12/2013 P. Vazquez (U. Santiago) 11
10 x 16 router 1 stage w 0 r 0 Data 0 FIFO_0 BCID= 0000 MUX 10 -to-1 FLIP FLOP Out 0 r 15 BCID= 1111 w 9 Data 9 12/12/2013 FIFO_9 P. Vazquez (U. Santiago) MUX 10 -to-1 FLIP FLOP Out 15 12
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