Nios implementation in CCD Camera for Pi of

Plan of presentation 1. Digital board of CCD camera for „Pi of the Sky”

Digital board of CCD camera for „Pi of the Sky” experiment

NIOS embedded processor and Avalon bus 1. Separate instruction and data buses – Harvard

RTL 8169 s PCI gigabit ethernet controller 1. Descriptor based buffer management – three

Custom PCI arbiter and Avalon bus multimastering 1. PCI arbitration can be controlled by

NIOS II and RTL 8169 s development board Bigger FPGA chip needed to implement

Future plans 1. Write whole camera software for NIOS II 2. Tests and comparisons

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Nios implementation in CCD Camera for "Pi of the Sky" experiment Photonics and Web Engineering Research Group Institute of Electronics Systems Warsaw University of Technology Maciej Kwiatkowski Supervisor: prof. dr hab. Ryszard Romaniuk dr Krzysztof Poźniak

Plan of presentation 1. Digital board of CCD camera for „Pi of the Sky” experiment 2. NIOS embedded processor and Avalon bus 3. RTL 8169 s PCI gigabit ethernet controller 4. Current solution vs Nios implementation 5. Custom PCI arbiter and Avalon bus multimastering 6. Future Plans

Digital board of CCD camera for „Pi of the Sky” experiment

NIOS embedded processor and Avalon bus 1. Separate instruction and data buses – Harvard architecture. 2. Instruction and data buses implemented as Avalon master ports. 3. The data master port connects to both memory and peripheral components, while the instruction master port connects only to memory components. 4. Memory can be shared and contains both instructions and data.

RTL 8169 s PCI gigabit ethernet controller 1. Descriptor based buffer management – three 1024 descriptor rings. 2. Address of descriptor rings is set by software in internal registers. 3. Descriptors consist of pointers to data buffers and additional flags. 4. Descriptors and buffers are placed in system memory. 5. Controller reads packet data from system memory and places it in the internal FIFO or it writes received packet from internal FIFO to system memory.

Current solution

Nios implementation

Custom PCI arbiter and Avalon bus multimastering 1. PCI arbitration can be controlled by CPU. 2. Data transmission requests from RTL 8169 s signalized by generating interrupt. 3. Interrupt subroutine should be placed in small on-chip memory. 4. Arbitration can be done on the Avalon bus side.

NIOS II and RTL 8169 s development board Bigger FPGA chip needed to implement NIOS with cache

Future plans 1. Write whole camera software for NIOS II 2. Tests and comparisons of different hardware versions (NIOS with or without cache) 3. Implementation of CCD state machine with FIFO and avalon slave port (after removing NIOS JTAG hardware)