Med Austron Controls Workshop 1 CNAO Power Supply

Med. Austron Controls Workshop 1 CNAO Power Supply Controls September 29, 2020 1 J. Gutleber

Logical Architecture Supervisory Control Ramp Definition Equipment Control Procedures DAQ DSS GFD Power Supply Local Control MTG September 29, 2020 2 J. Gutleber

Physical Architecture 16 bit samples over Ethernet at 10 k. Hz Supervisory Control Ramp Definition NI Compact RIO Power Supply Rack Equipment Control Procedures DAQ DSS GFD All waveforms downloaded over Ethernet (samples or curve segments) September 29, 2020 Optical or RJ 45 MTG 3 Power Supply (e. g. OCEM) Local Control 18 bit TTL Sampled waveforms At 5 to 50 k. Hz J. Gutleber

Support Software integrated with PVSS Datapoint definition Ramp definition DSS Configuration provision September 29, 2020 4 Ramp download GFD J. Gutleber

Digital Function Generator • Compact PCI crate • 1 CPU as controller • 1 FPGA for “anything IO” with • 96 pin SCSI-5 plug for output • Protocol to power supply logic controller uses 18 bit • 96 pin SCSI-5 plug for input from timing receiver card • 1 timing receiver card (by SIDEA) • 1 opto in, 1 22 bit TTL out to FPGA board September 29, 2020 5 J. Gutleber

Physical Layout (Example) UPS GFD Parallel bus to Power supply September 29, 2020 Control logic Compact RIO for acquiring current and environmental data Timing signal 6 J. Gutleber

Advantages • Entirely Commercial Off the Shelf • Separation of concerns • Responsibility of power supply functioning belongs to power supply company • Generic design • Wherever waveform production is needed • • • All waveforms are resident in function generator Simple integration with timing and B-train system Uses standard Ethernet apart from timing signals Good resolution and timing performance Support software can be purchased from CNAO • Waveform generation, distribution, configuration • Integrated with PVSS September 29, 2020 7 J. Gutleber

Disadvantages • Price • c. PCI crate, controller, FPGA boards, c. RIO, UPS • About 10’ 000 CHF per unit for control and acquisition • 2. 5 MIO CHF for control another 0. 5 MIO for DAQ • Space • Bulky, sometimes no space within power supply • Difficult to access in case of problems • Safety when opening power supply • Sometimes on top of power supply September 29, 2020 8 J. Gutleber

Same Design – Different technology • PC 104 with “anything IO” FPGA based IO • 600 CHF CPU, 300 CHF FPGA, 300 CHF timing receiver, rounded to 1’ 500 CHF for control • Complete solution should cost less than 3’ 000 CHF per unit. • Examples: mesanet. com (4 I 65), connect. Tech. com (Free. Form 104 Spartan based) Shop for more at http: //www. fpga-faq. com/FPGA_Boards. shtml • • NI single board Rio sb. RIO-96 xx O(1500 CHF) Keep simplicity of CNAO design Keep generic approach Lower price comparable to other solutions September 29, 2020 9 J. Gutleber

NI sb-RIO 96 xx September 29, 2020 10 J. Gutleber