IT Basics 10 Prof Rzvan Daniel Zota Ph
IT Basics 10 Prof. Răzvan Daniel Zota, Ph. D. The Bucharest University of Economic Studies Faculty of Cybernetics, Statistics and Economic Informatics zota@ase. ro http: //zota. ase. ro/itb
Contents • How microprocessors work: – Fetch-execute cycle – Access times – Performances 2
“Fetch-execute” cycle Memory AX CPU IP System bus 0000 1001 1000 1011 3
Fetch - a Memory AX CPU IP Instruction address RAM Address bus 1000: 0001 0000 1001 MAR = Memory addressing register 1000: 0010 1000 1011 Memory segmented address 4
Fetch - b Memory AX CPU Instruction code IR RAM Data bus IP++ 1000: 0001 0000 1001 MAR = Memory addressing register IR = Instruction register 1000: 0010 1000 1011 Segmented memory address 5
Execute - a Memory AX CPU IP Data address RAM Address bus 1000: 0001 0000 1001 MAR = Memory addressing register 1000: 0010 1000 1011 Segmented memory address 6
Execute - b Memory AX CPU Data: 1234 h IR RAM Data bus IP++ 1000: 0001 1000 1011 MAR = Memory addressing register IR = Instruction register Segmented memory address 1000: 0010 0011 0100 1000: 0011 0001 0010 7
Machine cycle “fetch – execute” Time - F Time - E Control unit Arithmetic/logic unit Fetch Execute 8
Main components of a microprocessor Registers Control unit Arithmetic/logic unit Clock CPU 9
The CPU is processing data stored in memory under the control of a program stored also in memory. Programs CPU Memory Data 10
Most of the instructions have an operation code and one or more operands. Instruction MOV AX, 1234 Operation code Operands 11
Memory addresses and values MEMORY 1000 : 3002 6723 1000 : 3004 12 34 1000 : 3006 7896 Value of var Displacement address (OFFSET) for var 12
Segmented address MEMORY 1000 : 3002 6723 1000 : 3004 12 34 1000 : 3006 7896 Segment address Offset 13
Building effective address from the segmented address 1000 : 3006 Segment address Displacement address (offset) 10000+ 3006 13006 - The segment address is shifted to the left with 4 bits – one hex digit - Add the displacement address - Finally we get the effective address using 20 bits (5 hex digits) 14
Memory hierarchy 15
- Slides: 15