Copyright c 2003 by Valery Sklyarov and Iouliia
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal
Example 2. A project that demonstrates an iteraction with external devices such as buttons, switchers and LEDs The circuit will be designed on the basis of TE-XC 2 Se prototyping board developed by Trenz Electronic with FPGA XC 2 S 300 E-6 -FT 256 1 1 0 L 1 B 1 bu tto 0 S 1. DIP. . S 8 L 2 ns L 3 L 4 D(7: 0) CPLD LEDs XC 9572 XL A(2: 1) B 4 P 16, L 13, J 14, G 15, F 14, E 15, B 16 M 10, T 10 Chip select Read/Write M 16 M 15 States of pushbuttons States of switchers Data for LEDs 00 01 10
entity led_but_sw is Port (clk : in std_logic; -- clock 48 MHz rst : in std_logic; -- reset cpld_rw : inout std_logic; -- cpld read/write cpld_cs : out std_logic; -- cpld chip select a : out std_logic_vector(2 downto 1); -- a – address d : inout std_logic_vector(7 downto 0) ); -- d – data end led_but_sw; architecture Behavioral of led_but_sw is signal state: std_logic_vector(3 downto 0); signal lled: std_logic_vector(7 downto 0); signal lpb : std_logic_vector(7 downto 0); signal dipswitch : std_logic_vector(7 downto 0); begin
process(clk, rst) -- process that describes a state sequencer begin if rst= '0' then state<=(others=> '0'); -- state = 00… 0 elsif rising_edge(clk) then state<= state + 1; -- increment state end if; end process; process(clk, rst) -- process that describes begin -- interactions with cpld if rst= '0' then cpld_cs <= '1'; elsif (clk='0' and clk'event) then
case state is -- for address 00 – reading the states of pushbuttons when "0000"=>a<= "00"; cpld_cs <= '1'; --passive cpld_rw <= '1'; --read when "0001"=>cpld_cs <= '0'; --active when "0010"=>lpb <= d; -- data from push buttons when "0011"=>cpld_cs <= '1'; --passive -- for address 10 – writing LEDs in the last process when "0100"=>a <= "10"; cpld_rw <= '0'; --write when "0101"=>cpld_cs <= '0'; --active when "0110"=>cpld_cs <= '1'; --passive -- for address 01 – reading the states of switchers when "0111"=>a <= "01"; cpld_cs <= '1'; --passive cpld_rw <= '1'; --read when "1000"=>cpld_cs <= '0'; --active when "1001"=>dipswitch <= d; -- data from push switchers when "1010"=>cpld_cs <= '1'; --passive when others =>cpld_cs <= '1'; --passive end case;
lled <= dipswitch; -- copy switchers to LEDs if (dipswitch(7)='1') then lled(3 downto 0)<= not lpb(3 downto 0); else null; end if; -- if S 7=0 swithers are copied to LEDs end process; -- if S 7=1 buttons are copied to LEDs process (lled, cpld_rw)-- writing LEDs to cpld begin -- i. e. writing LEDs to pushbuttons if (cpld_rw='0') then – if write is active d <= lled; -- writing LEDs to cpld else d <= "ZZZZ"; -- high impedance end if; end process; end Behavioral;
NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 48 MHz HIGH 50 %; NET "rst" LOC = "P 15" ; # individual LED NET "d<7>" LOC = "P 16" ; NET "d<6>" LOC = "L 16" ; NET "d<5>" LOC = "L 13" ; NET "d<4>" LOC = "J 14" ; 48 MHz NET "d<3>" LOC = "G 15" ; NET "d<2>" LOC = "F 14" ; NET "d<1>" LOC = "E 15" ; NET "d<0>" LOC = "B 16" ; NET "cpld_rw" LOC = "M 15" ; P 16, L 16, D(7: 0) L 13, J 14, NET "cpld_cs" LOC = "M 16" ; G 15, F 14, CPLD NET "clk" LOC = "T 9" ; E 15, B 16 XC 9572 XL A(2: 1) NET "a<2>" LOC = "M 10" ; M 10, T 10 NET "a<1>" LOC = "T 10" ; Chip select Read/Write M 16 M 15
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