Packages Package Declaration packagedeclaration package identifier is packagedeclarativepart

Package Declaration package_declaration : : = package identifier is package_declarative_part end [package] [identifier]; package_declarative_item

Example package data_types is subtype address is bit_vector(24 downto 0); subtype data is bit_vector(15

Package Body package_body : : = package body package_simple_name is package_body_declarative_part end [ package_simple_name

Example package body data_types is constant vector_table_loc : address : = X"FFFF 00"; function

$Use Clauses use_clause <= use selected_name { , selected_name } ; selected_name <= name.$

Example use work. data_types. address, work. data_types. data; variable data_word: word; variable next_address :

IEEE Standard Packages • std_logic_1164 multivalue logic system – std_ulogic, multivalued enumeration type –

std_logic_1164 functions • Overloaded logical operators: – and, nand, on, nor, xnor, not •

numeric_bit, numeric_std packages type UNSIGNED is array (NATURAL range <> ) of BIT; type

std_logic_arith, std_logic_unsigned, std_logic_signed • Developed by Synopsys • std_logic_arith similar to numeric_std – Conversion

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Packages

Package Declaration package_declaration : : = package identifier is package_declarative_part end [package] [identifier]; package_declarative_item : : = subprogram_declaration | type_declaration | subtype_declaration | constant_declaration | alias_declaration | use_clause

Example package data_types is subtype address is bit_vector(24 downto 0); subtype data is bit_vector(15 downto 0); constant vector_table_loc : address; function data_to_int(value : data) return integer; function int_to_data(value : integer) return data; end data_types; variable PC : work. data_types. address;

Example package body data_types is constant vector_table_loc : address : = X"FFFF 00"; function data_to_int(value : data) return integer is body of data_to_int end data_to_int; function int_to_data(value : integer) return data is body of int_to_data end int_to_data; end data_types;

$Use Clauses use_clause <= use selected_name { , selected_name } ; selected_name <= name.$

Use Clauses use_clause <= use selected_name { , selected_name } ; selected_name <= name. (identifier | character_literal | operator_symbol | all)

Example use work. data_types. address, work. data_types. data; variable data_word: word; variable next_address : address; use ieee. std_logic_1164. all;

IEEE Standard Packages • std_logic_1164 multivalue logic system – std_ulogic, multivalued enumeration type – std_ulogic_vector – std_logic, resolved multivalued enumeration type – std_logic_vector

std_logic_1164 functions • Overloaded logical operators: – and, nand, on, nor, xnor, not • • To_bit(s, xmap) To_bitvector(s, xmap) To_Std. ULogic(b) To_Std. Logic. Vector(x) To_Std. ULogic. Vector(x) To_X 01(x), To_X 01 Z(x), To_UX 01(x) rising_edge(s), falling_edge(s) is_X(s)

numeric_bit, numeric_std packages type UNSIGNED is array (NATURAL range <> ) of BIT; type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; • • • Defines all VHDL operators on types unsigned and signed Shift, Rotate functions Conversion (integer/natural <=> signed unsigned) functions Edge detection Match functions

std_logic_arith, std_logic_unsigned, std_logic_signed • Developed by Synopsys • std_logic_arith similar to numeric_std – Conversion functions between signed/unsigned and std_logic_vector • std_logic_unsigned extended functionality – Unsigned operations on type std_logic_vector • std_logic_signed extended functionality – Signed operations on type std_logic_vector