Low Voltage Efficient Fused Multiply Add Andrew Nelson

Motivation • Power density of CMOS increasing with each generation • Battery life increasingly

Previous Work • Based on Fused Multiply-Adders • Embarrassingly Parallelizable Designs have power/area/performance tradeoff

Fused Multiply-Adder • Optimizes performance of A*B+C with one rounding • Created by IBM

Synthesis Design Flow • Synthesis automatically minimizes power/delay/area based on input constraints • Standard

Tools • Free. PDK with 45 nm HP ASU PTM transistor models • Encounter

Conclusion • Mobile computing has different design tradeoffs vs. high performance computing • Operating

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Low Voltage Efficient Fused Multiply Add Andrew Nelson, Emmanuel Chao April 30, 2012 Spring 2012 - EE 241 Term Project

Motivation • Power density of CMOS increasing with each generation • Battery life increasingly important for mobile applications

Previous Work • Based on Fused Multiply-Adders • Embarrassingly Parallelizable Designs have power/area/performance tradeoff • Failed to address <1 v designs. S. Galal, M. Horowitz, ”Energy-Efficient Floating-Point Unit Design, ” Computers, IEEE Transactions on, vol. 60, no. 7, pp. 913 -922, July 2011.

Fused Multiply-Adder • Optimizes performance of A*B+C with one rounding • Created by IBM in 1990 • Used heavily for DSP/graphics • Easily paralyzed

Synthesis Design Flow • Synthesis automatically minimizes power/delay/area based on input constraints • Standard cells limited to nominal voltage • Need to characterize standard cells

Tools • Free. PDK with 45 nm HP ASU PTM transistor models • Encounter Library Characterizer to recharacterize standard cells • Encounter RTL Compiler for Synthesis

Scaling Lower Voltage

Optimal Voltage Maximize FOM for each N

Conclusion • Mobile computing has different design tradeoffs vs. high performance computing • Operating at <1 v makes sense when power is more important than area