LOGO Chapter 1 Interrupt handling hardware interrupt Under

LOGO Chapter 1 Interrupt handling

hardware interrupt Under x 86, hardware interrupts are called IRQ's. When the CPU receives an interrupt, it stops whatever it's doing (unless it's processing a more important interrupt, in which case it will deal with this one only when the more important one is done), saves certain parameters on the stack and calls the interrupt handler.

Hardware interrupts architecture in x 86 IRQ Numbers rior to plug-and-play devices, users had to set IRQ values of devices manually when adding the device, such as a modem or printer, to a system. The following list of IRQ numbers specifies what each of the 16 IRQ lines are used for.

Example IRQ signal sources IRQ Number Typical Use Description System timer This interrupt is reserved for the internal system timer. It is never available to peripherals or other devices. IRQ 1 Keyboard This interrupt is reserved for the keyboard controller. Even on devices without a keyboard, this interrupt is exclusively for keyboard input. IRQ 2 Cascade interrupt for IRQs 815 This interrupt cascades the second interrupt controller to the first. Second serial port (COM 2) The interrupt for the second serial port and often the default interrupt for the fourth serial port (COM 4). First serial port (COM 1) This interrupt is normally used for the first serial port. On devices that do not use a PS/2 mouse, this interrupt is almost always used by the serial mouse. This is also the default interrupt for the third serial port (COM 3). IRQ 0 IRQ 3 IRQ 4

IRQ 5 Sound card This interrupt is the first choice that most sound cards make when looking for an IRQ setting. IRQ 6 Floppy disk controller This interrupt is reserved for the floppy disk controller. IRQ 7 First parallel port This interrupt is normally reserved for the use of the printer. If a printer is not being used, this interrupt can be used for other devices that use parallel ports. IRQ 8 Real-time clock This interrupt is reserved for the system's real-time clock timer and can not be used for any other purpose. IRQ 9 Open interrupt This interrupt is typically left open on devices for the use of peripherals. IRQ 10 Open interrupt This interrupt is typically left open on devices for the use of peripherals. IRQ 11 Open interrupt This interrupt is typically left open on devices for the use of peripherals. PS/2 mouse This interrupt is reserved for the PS/2 mouse on machines that use one. If a PS/2 mouse is not used, the interrupt can be used for other peripherals, such as network card. IRQ 12

How hardware interrupt works in PC? A table of interrupt vectors (pointers to routines that handle interrupts). Use of the interrupt vector table can be triggered by three types of events: hardware interrupts, software interrupts and exceptions, which together are often simply referred to as "interrupts". In total up to 256 of these can be defined, each with their own unique identifier which is called a vector. On PCs, the interrupt vector table consists of 256 4 byte pointers, and resides in the first 1 K of addressable memory. (after 80386, the interrupt table can be anywhere in the memory, specified by a register called IDTR) Each interrupt number is reserved for a specific purpose. For example, 16 of the vectors are reserved for the 16 IRQ lines.

The mapping between IRQs and Interrupt Vector Table This is a list showing what the different IRQ lines in the system is going to be used for. Its also listed what the different IRQ are normally used for, and what Interrupt they are going to be routed to. Here is the list: IRQ Usage IRQ IDT Normaly Used For Most Likely To Be Used For NMI 1 02 h Memory parity control 0 50 h Systemtiming 1 51 h Keyboard 2 52 h The PIC-2 is cascaded to this IRQ The PIC-2 cascade IRQ 8 -15 is connected to PIC-2. When PIC-2 receives an interrupt request it uses its own IRQ line to signal PIC-1. When the lowest IRQ has the highest priority, any interrupt request (8 -15) coming through the PIC-2 cascade must have a higher priority than interrupt request from 3 to 7. This table has the highest IRQ priority on the top. 8 53 h RTC Available for Pn. P Configuration 9 54 h Network Available for Pn. P Configuration 10 55 h Quaternary IDE Available for Pn. P Configuration 11 56 h Quaternary IDE / Tertiary IDE Available for Pn. P Configuration 12 57 h Tertiary IDE Available for Pn. P Configuration 13 58 h Exceptions in FPU calculations Available for Pn. P Configuration 14 59 h Primary IDE Available for Pn. P Configuration 15 5 Ah Secondary IDE Available for Pn. P Configuration 3 5 Bh COM 2 Available for Pn. P Configuration 4 5 Ch COM 1 Available for Pn. P Configuration 5 5 Dh LPT Available for Pn. P Configuration 6 5 Eh Floppy Available for Pn. P Configuration 7 5 Fh LPT Available for Pn. P Configuration

When an hardware interrupt occurs 1. The CPU stops what it is doing 2. Store its return address (like a call) and status (flags, etc) 3. Retrieve the pointers in the IVT (Interrupt vector table) 4. Jump to the address of the pointer 5. Executing code in the handler 6. The handler usually return by IRET 7. IRET returns the saved address and status (flags) 8. CPU continues its execution from where it is stopped.

Software Interrupt The address in a IVT can be also called by programs, using INT n, where n is the interrupt number In a protected O. S. software interrupt instructions are used as a trap instruction. O. S. uses it to open a gate for user programs to communicate so that protection mode changed can be invoked.

The difference between CALL and INT In x 86 assembly language, there are the call (call a subroutine) and ret (return from subroutine) instructions. Before transferring control to the subroutine, call pushes the segment offset address of the instruction following the call onto the stack; ret pops this value off the stack, and jumps to it, effectively returning the flow of control to that part of the program. . There also two similar instructions, int (interrupt), which saves the current register values on the stack, then performs a far call, except that instead of an address, it uses an interrupt vector, an index into a table of interrupt handler addresses. The matching return from interrupt instruction is iret, which restores the register values after returning. Soft Interrupts of the type described above are used by some operating systems for system calls, and can also be used in debugging hard interrupt handlers. Hard interrupts are triggered by external hardware events.