Independent Study Presentation Title Name Name and Name

Independent Study Presentation Title Name, Name and Name School of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea. Abstraction & Introduction • Make SSDs faster Magnetic storage devices such as Hard Disk Drives (HDDs) have been the de-facto standard mass-storage devices. in most electronic devices. • People always wants to more faster storage devices. • SSD is fast ! • In the multi-channel / multi-way architecture, it is necessary to transform the conventional logical address structure to handle the channel and way mapping issue. For this reason, we add two extra fields called C field and W field. • No matter what structure is chosen, the bit width of the B field should be reduced for allocating part of its bits to the two additional fields. • We emphasize the scalable design of a address-mapping table. More specifically, we design the mapping table to keep the nature of the FTL-SS as much as possible. • Example 2: each NFM has its own log blocks which can be accessed by other NFMs. If a page copying occurs across the ways, a page is read from one NFM by the NFM controller and then sent to the other NFM. • A SSD is a fast, silent and low-power storage device that uses flash memory. • Flash memory is non-volatile computer storage that can be electrically erased and reprogrammed. • We must execute erase operation to flash memory before write operation. Experiment & Result • A erase operations consume long time. • A unit of one erase operation is bigger than read/write operation. • Idle task is closely related to erase operation. Access time Read Write Erase 10. 24 us (2 KB) 25 us 200 us 2 ms (2 KB) (128 KB) 49. 6 ms (2 KB) Media DRAM NAND Flash Disk • We executed trace driven simulation using So. C designer. Normal FTL and Oracle -aware channel utilization (OCU): is defined as the CU of an FTL over the CU of the oracle FTL for comparing the performance of an FTL with that of the oracle FTL. Background & Related Work • SSD Structure One bus to one channel One NAND FLASH chip A unit of erase A unit of read/write A unit of data length • FTL (Flash Translation Layer) 1 2 3 Reference Figure (1) Out-of-place scheme figure (2) FTL (BAST) figure (3) Full merge Figure (4) Flowchart of BAST write * Select Prey can happen. [1] 배영현, 고성능 플래시 메모리 SSD(Solid State Disk) 설계 기술. 정보과학회지, 2007. [2] Hynix Semiconductor, Intel Corporation, Micron Technology, Inc. , Phison Electronics Corp. , Sony Corporation, Spansion, STMicroelectronics. Open NAND Flash Interface Specification. 2008 [3] Jesung Kim, Jong Min Kim, Sam H. Noh, Sang Lyul Min and Yookun Cho, A SPACE-EFFICIENT FLASH TRANSLATION LAYER FOR COMPACTFLASH SYSTEMS. IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, MAY 2002. [4] SANG-WON LEE, DONG-JOO PARK, TAE-SUN CHUNG, DONG-HO LEE, SANG-WON PARK, and HA-JOO SONG, A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. ACM Transactions on Embedded Computing Systems, Vol. 6, No. 3, 2007. [5] Jeong-Uk Kang, Heeseung Jo, Jin-Soo Kim, Joonwon Lee, A Superblock-based Flash Translation Layer for NAND Flash Memory. 2007. [8] Sungjin Lee, Dongkun Shin, Young-Jin Kim, LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems. 2008. [6] ERAN GAL and SIVAN TOLEDO, Algorithms and Data Structures for Flash Memories. ACM Journal. 2005. [7] Intel, Understanding the Flash Translation Layer (FTL) Specification. 1998. [8] Richard Golding, Peter Bosch, Carl Staelin, Tim Sullivan, and John Wilkes, Idleness is not sloth. [9] Sung-Yong Bang, Kwanhu Bang, Sungroh Yoon and Eui-Young Chung, Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 9, 2009. [10] Sai Krishna Mylavarapu, IMPROVING APPLICATION RESPONSE TIMES OF NAND-FLASH BASED SYSTEMS. 2008. [11] Feng Chen, David A. Koufaty and Xiaodong Zhang, Understanding Intrinsic Characteristics and System Implications of Flash Memory based Solid State Drives. SIGMETRICS. 2009. [12] Sang-Hoon Park, Seung-Hwan Ha, Kwanhu Bang, and Eui-Young Chung, "Design and analysis of flash translation layers for multi -channel NAND flash-based storage devices", Consumer Electronics, IEEE Transactions on vol. 55, no. 3, pp. 1392 - 1400, 2009. 8. [13] http: //en. wikipedia. org/wiki/NAND_FLASH, http: //en. wikipedia. org/wiki/Solid-state_drive DTL Yonsei University.