EE 194 Advanced VLSI Spring 2018 Tufts University

EE 194: Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel. grodstein@tufts. edu Course introduction EE 194 Joel Grodstein 1

Logistics • Class web page: http: //www. ee. tufts. edu/ee/194 VLS EE 194 Joel Grodstein 2

Prerequisites • VLSI: – – Basic digital design (gates, flip flops, Boolean algebra) Basic idea of finite state machines EE 103 or equivalent Basic architecture • Computer science – One of your homeworks will be writing a computer program in C or C++. Nothing fancy, but you have to be able to get code written & working EE 194 Joel Grodstein 3

What is this class about? • First time this class is offered • Small class means we can be flexible in tailoring it to students' interests. – A few topics we'll definitely cover, and several more that we may or may not. We may add others on request. – The pace will be whatever is needed so that the large majority of people understand most everything. EE 194 Joel Grodstein 4

Professor • Joel Grodstein – Half-time lecturer at Tufts (in my 2 nd semester) – 25 years of experience in VLSI (retired) at Intel, HP, Compaq, Digital Equipment, Evans & Sutherland – joel. grodstein@tufts. edu – Office Halligan extension #11 – Office hours 1 hour before class. Other times by arrangement. – Feel free to use the office hours, even just to chat about the computer industry. 5

The semester in detail • Here's our detailed list of potential topics EE 194 Joel Grodstein 6

Process scaling • Process scaling has been the engine driving the computing industry for many years – – That era is ending What was scaling, and why is it ending? How does scaling affect power? Speed? Old prediction: chips would turn into nuclear reactors; did not come true . Why not? EE 194 Joel Grodstein 7

Static timing analysis • What is it? – Given a collection of gates, each with a delay (but paying little or no attention to logic function) – Usually no input pattern given (hence "static") – Predict worst-case timing on every node & see if the chip will operate at frequency • We will: – – Understand the basics of gate delay & why it can be hard to predict Understand timing constraints for flops and latches Understand the basics of speed binning, and its interaction with STA Manufacturing is cool – because money is cool • For those who went through the STA lectures in last spring’s CAD class, we’ll go deeper this time EE 194 Joel Grodstein 8

Clocking • Understand conditional clocks: – usage for power savings and for functionality – electrical implementation – static-timing analysis constraints for conditional clocks • Clock distribution – – Sending one signal to a billion destinations is really hard While minimizing power, skew, jitter, … We’ll learn various distribution strategies And clock islands and ways to cross them • For those who went through the STA lectures in last spring’s CAD class, we’ll go deeper this time EE 194 Joel Grodstein 9

Validation • How do you know if your Verilog design is correct? – – – Lots of validation Usually not covered well in university courses Not thought of as glamorous enough But validation is where the most jobs are And some would argue it’s more fun than design • May bring in a guest speaker from Cavium/Marvell EE 194 Joel Grodstein 10

DVFS • Discrete Voltage and Frequency Switching – – – – Used by most processors nowadays, to save power To not have your chip be a nuclear reactor We’ll cover the power savings The effect on STA The effect on speed binning The effect on clock islands Physical issues in delivering lots of variable voltages to a die EE 194 Joel Grodstein 11

Latching and scan • We need tests for chips with 10 M gates. – Any transistor or wire can be broken. How do you write the tests to test so many things? – And your test set should be reasonably minimal • Learn about scan and ATPG, and how they affect flop design EE 194 Joel Grodstein 12

VLSI futures • Where will VLSI be in 10 -20 years? • Learn about a few interesting possible futures – – Dark silicon & heterogeneous processors Timed digital logic Stochastic digital logic Reprogramming bacteria to compute EE 194 Joel Grodstein 13

For each major topic… • 2 -4 lectures covering the topic in a "reasonable" amount of detail (nowhere near exhaustive) • Assignments: – Most unit has a set of homework problems; one or two of these should be replace by a one-on-one oral quiz. Some have extracredit problem(s) as well – The STA unit also has a computer program – Two of the units have a research paper that we’ll discuss in class • No midterm or final exam currently planned EE 194 Joel Grodstein 14

What other topics would be nice? EE 194 Joel Grodstein 15

Logistics • No book… just foils, notes & the research papers – I usually teach on Powerpoint slides (like this one. . . ) • Tools: – Hand in HW via Provide. – Get grades back via Trunk. – E-mail to joel. grodstein@tufts. edu for other questions. EE 194 Joel Grodstein 16