Designing State Machines SQRT controller Lecture L 9

Designing State Machines SQRT controller Lecture L 9. 2 a Section 9. 2

SQRT Controller • Mealy and Moore Machines • SQRT Controller

A canonical sequential network

A Mealy state machine

A Moore state machine

SQRTctl

Lab 8

MODULE SQRTctl interface(Clk, Clear, lteflg, strt -> ald, sqld, dld, outld); TITLE 'Control Unit for square root algorithm' DECLARATIONS " INPUT PINS " Clk PIN; lteflg PIN; Clear PIN; start PIN; " " clock <= flag clear GCD starts when start = 1 " OUTPUT PINS " ald, sqld, dld, outld PIN; " reg load signals

A Moore state machine

Q 1. . Q 0 NODE ISTYPE 'reg buffer'; Q = [Q 1. . Q 0]; " 2 -bit state vector " Definitions QSTATE = [Q 1, Q 0]; start = [0, 0]; test = [0, 1]; update = [1, 0]; done = [1, 1]; state_diagram QSTATE state start: if strt then test else start; state test: if lteflg then update else done; state update: goto test; state done: goto done;

A Moore state machine

EQUATIONS WHEN QSTATE {ald == start then = 1; sqld = 0; == test then = 0; sqld = 0; == update then = 0; sqld = 1; == done then = 0; sqld = 0; Q. C = Clk; Q. AR = Clear; END SQRTctl " a <- SW dld = 0; outld = 0; } dld = 0; " dld = 1; " dld = 0; outld = 0; } sq <- sq + del; del <- del + 2 outld = 0; } out <- (del - 1)/2 outld = 1; }

Lab 8