CLB Current status and development IFIC CSIC Universidad
CLB: Current status and development IFIC (CSIC – Universidad de Valencia) 13 Nov, 2013
TDC: MODIFICATIONSl & OPEN QUESTIONS • Pulse width larger than 255 ns will not be discarded? : 1. - Should we change the data format? More bits for width? 2. - Should we split it in differents hits? ? FIFO 516 10 30 20 15 50 T_STAMP (ns) WIDTH (ns) 30 10 60 254 60 16 626 15 Pulse width = “ 1111” reserved for new time slice 2
TDC: MODIFICATIONSl & OPEN QUESTIONS Pulse width larger than 255 ns will not be discarded • What about if change of time slice is during the width? ? 1. Should we stored in the previous time slice? ? FIFO CH 1 New time slice 516 10 30 20 200 15 316 50 T_STAMP WIDTH 30 10 60 254 60 16 Special_mark 255 366 15 2. Should we split it in differents time slices ? ? 3. Other options… 3
l STATE MACHINE: TEST TDC 0 Fifo TDC 30 • Hydro memory soon State Machine • TDC memory integrated HYDRO MEMORY S M M Management & Control Fifo S M M Management & Control ADC Hydrophone Fifo 31 PMTs 31 TDCs State Machine TDC MEMORY FIFOs FOR JAVA TEST M M WB Crossbar M (1 x 8) M M S UART Debug RS 232 JAVA APLICATION (GENOVA) 4
STATE MACHINE: l. CURRENT DESIGN TDC FIFO TIME SLICE 1 NEW TIME SLICE 2 Time Stamp (32 bits) Pulse Width (8 bits) Time stamp 1 Width 1 Time stamp 2 Width 2 Time stamp 3 Width 3 ……………. “ 000000” + Absolute time (28 bits) “ 1111” Absolute time (40 bits) Time stamp 1 Width 1 Time stamp 2 Width 2 Time stamp 3 Width 3 ……………. 5
l INTEGRATION DONE • 2 nd LM 32 • TDC and state machine • MULTIBOOT NOT YET (But soon) • White Rabbit • Hydro • 4 x I 2 C • UART • 2 x I 2 C • SPI 6
FIRMWARE OVERVIEW State Machine Management & Config. Tx_data 2 buf Tx Stream Select Tx_pkt 2 mac Pause Frame Tx. Packet Buffer 32 KB Flags Rx. Port_m Tx. Port 1 Tx. Port 2 Fifo TDC 30 S Management & Control ADC Fifo S Management & Control Multiboot Tx. Port_m S M M Management & Control Nano Beacon M S WB Crossbar M M (1 x 8) M M M Xilinx Kintex-7 M MEM S Data Control Wishbone bus M M WB Crossbar (3 x 2) M S S M 2 nd CPU LM 32 S UTC time & Clock (PPS, 125 MHz) Point to Point interconnection TDC 0 31 PMTs Fifo Multiboot Hydro Flags Rx. Port 1 Rx. Port 2 State Machine Rx_buf 2 data Rx Stream Select Rx_mac 2 buf Rx. Packet Buffer 64 KB 31 TDCs Time Slice Start IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Hydrophone White Rabbit S SPI UART SPI Flash Debug RS 232 S I 2 C Temp S I 2 C Debug LEDs S GPIO Compass Tilt Comunication Interfaces 7 7
THANKS FOR YOUR ATTENTION!
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