Calculator Design n Calculator has 4 functions Add

Calculator Design n Calculator has 4 functions: èAdd èSubtract èShift left èShift right n Calculator can handle 4 requests in parallel èAll 4 requestors use separate input signals èAll requestors have equal priority

Calculator design n Input/Output description c_clk req 1_cmd_in<0: 3> out_resp 1<0: 1> req 1_data_in<0: 31> req 2_cmd_in<0: 3> req 2_data_in<0: 31> req 3_cmd_in<0: 3> req 3_data_in<0: 31> req 4_cmd_in<0: 3> req 4_data_in<0: 31> reset<0: 7> out_data 1<0: 31> calc_top out_resp 2<0: 1> out_data 2<0: 31> out_resp 3<0: 1> out_data 3<0: 31> out_resp 4<0: 1> out_data 4<0: 31>

Calculator Design n I/O Description èInput commands: – 0 - No-op – 1 - Add operand 1 and operand 2 – 2 - Subtract operand 2 from operand 1 – 5 - Shift left operand 1 by operand 2 places – 6 - Shift right operand 1 by operand 2 places èInput Data – Operand 1 data arrives with command – Operand 2 data arrives on the following cycle

Calculator Design n Outputs èResponse line definition – 0 - no response – 1 - successful operation completion – 2 - invalid command or overflow/underflow erro – 3 - Internal error èData – Valid result data on output lines accompanies response (same cycle)

Calculator Design n Other information èClocking – – When using a cycle simulator, the clock should be held high (c_clk in the calculator model) The clock should be toggled when using an event simula èCalculator priority logic – Priority logic works on first come first serve algorithm – Priority logic allows for 1 add or subtract at a time and one shift operation at a time

Calculator Design n Input/Output timing req 1_cmd_in<0: 3> req 1_data_in<0: 31> out_resp 1<0: 1> out_data 1<0: 31>