A Reconfigurable Architecture for Multicontext Application Remy Eskinazi

A Reconfigurable Architecture for Multi-context Application Remy Eskinazi Sant´Anna Federal University of Pernambuco – UFPE GRECO – Engineering Computer Group GRECO - CIn - UFPE 1

Motivation n Hardware/Software Codesign platform for fast prototyping of digital systems Education n Hardware/Software Codesign n Reconfigurable systems Industrial prototyping of digital systems GRECO - CIn - UFPE 2

Chameleon Design Flow Keil System Specification Vision/51 Partitioning HW/SW VHDL Hardware description Behavioural Synthesis simulation RT description C Software algorithm Compilation debugging Executable code Logic Synthesis (Netlist) Mapping CHAMELEONGRECO board- CIn - UFPE 3

Hw/Sw Configuration programs flow hardware software Source - vhdl Source - C XILINX tools Keil Compiler . hex Parser . bin Merge. mrg GRECO - CIn - UFPE 4

Codesign Architecture Core Interfaces Serial Biosensors Image Process bitstream Core Selector Signal Process FPGA Acoustic Biosensor Temperature m. C Reconfigurable Hardware PC (Database) Codesing Architecture GRECO - CIn - UFPE 5

Chameleon Architecture RD WR INT 0 ALE PEN WS BUSY/RDY INIT DONE PROG data 8 hardware 61 I/O ports Microcontroller host Serial comm. software FPGA (84 pins) address XC 4003 E->XC 4013 16 80 C 32 80 C 51 87 C 51. . RAM (64 K) EPROM (64 K) Shared memory GRECO - CIn - UFPE 6

Hardware Reconfigurable Component XC 4000 XILINX Architecture Component 40003 E 4005 4006 4008 E 4010 E 4013 E Logic Cells 238 466 608 770 950 1, 368 Max Logic Gates 3 K 5 K 6 K 8 K 10 K 13 K Configurable Logic Blocks (CLBs) C 1 C 2 C 3 C 4 H 1 DIN S/R EC S/R Control G 4 G 3 G 2 G 1 F 4 F 3 F 2 F 1 G Func. Gen. DIN F' G' EC RD 1 Y G' H' Slew Rate Control S/R Control DIN D SD F' G' D Q Passive Pull-Up, Pull-Down Vcc Output Buffer Q Pad H' Input Buffer H' K Q H' H Func. Gen. F Func. Gen. SD D F' 1 Q EC RD X GRECO - CIn - UFPE D Delay I/O Blocks (IOBs) 7

Monitor Program Core Download Yes End File? Yes Another File? Not Returns to monitor Software and hardware cores End Not Monitor transfer control to the application Switch Ram Configure FPGA Execute code Application GRECO - CIn - UFPE 8

Monitor Program Core N. . . Core 2 56 kbytes (Hardware Cores) Core 1 2 kbytes Monitor variables 2 kbytes monitor mirror 2 kbytes User program (Sofware Cores) Vectors GRECO - CIn - UFPE 9

Chameleon Supervisory GRECO - CIn - UFPE 10

Chameleon Board GRECO - CIn - UFPE 11

Conclusions n n A flexible low cost prototyping board has been developed; The platform shows to able to implement small designs in a hardware/software codesign approach; The board has shown to be able to reduce the time during the development process of digital systems ; Academic case studies has been implemented on the platform. GRECO - CIn - UFPE 12

(4) (9) (8) (1) Chameleon. I FPGA (5) (3) AC / DC Oscillator (2) (7) (6) ) ) ) ) Chameleon Platform Oscillator Circuit Board Circuit Power Board Reset System Power On/Off Serial Communication Crystal Resonant Reference Crystal Resonant Work FIA System GRECO - CIn -FIGURE UFPE 7 - Case study architecture 13