Zynq intr part 3 Copyright 2014 Xilinx Content

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Zynq intr – part 3 © Copyright 2014 Xilinx.

Zynq intr – part 3 © Copyright 2014 Xilinx.

Content Description of the effects on interrupt mapping when migrating a project from a

Content Description of the effects on interrupt mapping when migrating a project from a Vivado 2013. x project to a Vivado 20143. x project. Description of the special case for a single interrupt mapping © Copyright 2014 Xilinx.

Special cases Migrating a project from 2013. 4 to 2014. x Let’s take a

Special cases Migrating a project from 2013. 4 to 2014. x Let’s take a project used in 2013. 4 and migrate it to 2014. 3 © Copyright 2014 Xilinx.

The upgrade process The IP upgrade is automated by Vivado. The Concat block gets

The upgrade process The IP upgrade is automated by Vivado. The Concat block gets updated to the latest version in 2014. x The PS 7 block gets updated to the latest version in 2014. x © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x Concat block The IP upgrade means a

Upgrade from 2013. x to 2014. x Concat block The IP upgrade means a change of order for the interrupts compared to the order in 2013. x Concat in 2014. x © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x IRQ_F 2 P_MODE parameter Let’s look at

Upgrade from 2013. x to 2014. x IRQ_F 2 P_MODE parameter Let’s look at the parameter value for a project that was migrated from 2013. x to 2014. x: The parameter value is now “REVERSE”. © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x Generated PS 7 source file internal interrupt

Upgrade from 2013. x to 2014. x Generated PS 7 source file internal interrupt vector As a result of the IRQ_F 2 P_MODE parameter value being “REVERSE”, the internal irq_f 2 p_i vector is now representing the mapping from 2013. x: © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x © Copyright 2014 Xilinx.

Conclusion for an upgrade To keep the 2013. x original interrupt mapping it is

Conclusion for an upgrade To keep the 2013. x original interrupt mapping it is necessary to reverse the input interrupt order on the concat block. The “REVERSE” parameter then takes care of arranging the mapping as was previously implemented in 2013. x. © Copyright 2014 Xilinx.

Test Design Let’s remove the concat block and use a single interrupt: © Copyright

Test Design Let’s remove the concat block and use a single interrupt: © Copyright 2014 Xilinx.

2013. x As there is no concat block involved it is a straight-forward mapping.

2013. x As there is no concat block involved it is a straight-forward mapping. The PS 7 code is as previously seen: In 0 is mapped to ID 91. © Copyright 2014 Xilinx.

2014. x The IRQ_F 2 P_MODE parameter from the PS 7 source file is

2014. x The IRQ_F 2 P_MODE parameter from the PS 7 source file is set to “DIRECT”. In 0 is therefore mapped to ID 61. © Copyright 2014 Xilinx.

In 2014. x © Copyright 2014 Xilinx.

In 2014. x © Copyright 2014 Xilinx.

Migrating the project form 2013. x to 2014. x The PS 7 parameter IRQ_F

Migrating the project form 2013. x to 2014. x The PS 7 parameter IRQ_F 2 P_MODE is now set to “REVERSE”: © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x Generated PS 7 source file internal interrupt

Upgrade from 2013. x to 2014. x Generated PS 7 source file internal interrupt vector As a result of the IRQ_F 2 P_MODE parameter value being “REVERSE”, the internal irq_f 2 p_i vector is now representing the mapping from 2013. x: © Copyright 2014 Xilinx.

Upgrade from 2013. x to 2014. x In 0 mapping did not change compared

Upgrade from 2013. x to 2014. x In 0 mapping did not change compared to the implementation in 2013. x because the IRQ_F 2 P_MODE parameter was set to “REVERSE”. © Copyright 2014 Xilinx.

Follow Xilinx facebook. com/Xilinx. Inc twitter. com/Xilinx. Inc © Copyright 2014 Xilinx. youtube. com/Xilinx.

Follow Xilinx facebook. com/Xilinx. Inc twitter. com/Xilinx. Inc © Copyright 2014 Xilinx. youtube. com/Xilinx. Inc

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