Zed Board Xilinx Zynq7000 AP So C XC
Zed. Board Xilinx Zynq-7000 AP So. C XC 7 Z 020 -CLG 484 HDMI 輸出 VGA (12 -bit Color) 10/100/1 G 乙太網路 音訊線路輸入/輸出、耳機、麥克風 Boot Jumper 主配置:QSPI Flash 輔助配置選項:Cascaded JTAG / SD Card Power 12 V @ 5 A AC/DC 1 個 LPC FMC (FPGA Mezzanine Card) 128 x 32 OLED 顯示板 7 個按鈕 (2 PS, 5 PL) 2 個重置按鈕 (1 PL, 1 PS) Pmod (sensor)介面 8 個 User LEDs 8 個 dip/slide 開關 (PL)
AD 9361 l RF 2 × 2 transceiver with integrated 12 -bit DACs and ADCs l TX band: 47 MHz to 6. 0 GHz l RX band: 70 MHz to 6. 0 GHz l Supports TDD and FDD operation l Tunable channel bandwidth: 200 k. Hz to 56 MHz
FPGA design flow Design Specification Synthesis HDL Implementation Simulation Verify on the board
Vivado 點選Next
Vivado 選擇RTL Projext
Vivado 點選Finish完成專案建立
Vivado 在Project Manager視窗中,選擇Source子視窗,在空白處或任意資料夾上右擊,選擇Add Sources 選擇Add or Create Design Sources,點選Next。
Vivado 新增Verilog模擬檔案(Simulation Source)
Vivado 行為模擬 在Flow Navigator視窗中點選Run Simulation - Run Behavioral Simulation 即可進行行為模擬
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