Xilinx 95009500 XL CPLD Testing CNGS 2009 TEMPEMI

Xilinx 9500/9500 XL CPLD Testing CNGS 2009 TE/MPE/MI Radiation Working Group 18 th September 2009 B. Todd, M. Zerlauth, I. Romera, A. Castaneda 0 v 4

CPLDs Used in the Interlock Systems Beam Interlock System (5 V) 500 nm XC 95288 x 300 UA, UJ, RR (3. 3 V) 350 nm XC 95288 XL x 34 UA, SR Power Interlock Controllers (5 V) 500 nm XC 95144 x 36 UA, UJ, RR 95288/144 failure = maintenance required = not machine critical 95288 XL failure = can compromise safety N. B. Whole BIS is redundant = needs two identical failures during a mission 95288 XL in VME chassis TE/MPE/MI has installed a Radiation Test Bench in CNGS XC 95144 x 32 Almost = # in LHC XC 95288 XL x 32 benjamin. todd@cern. ch

CPLDs Used in the Interlock Systems Beam Interlock System (5 V) 500 nm XC 95288 x 300 UA, UJ, RR (3. 3 V) 350 nm XC 95288 XL x 34 UA, SR Power Interlock Controllers (5 V) 500 nm XC 95144 x 36 UA, UJ, RR 95288 failure = maintenance required = not machine critical 95288 XL failure = compromises safety N. B. Whole BIS is redundant = needs two identical failures during a mission 95288 XL in VME chassis TE/MPE/MI has installed a Radiation Test Bench in CNGS XC 95144 x 32 Almost = # in LHC XC 95288 XL x 32 benjamin. todd@cern. ch

Results Without adjustment of values from monkey program! XC 95288 XL - 3. 3 V - 350 nm Daniel - you should adjust for your factor! 4 x 1012 >20 Me. V Hadrons per cm 2 9972 Single Event Effects observed in all devices 80% = FALSE DUMP 1 device = 1 cm 2 20% LOSS OF REDUNDANCY 8 x 10 -11 Glitches per device, per >20 Me. V Hadron 79 Grays Total Dose still OK XC 95144 - 5 V - 500 nm 8 x 1011 >20 Me. V Hadrons per cm 2 9 Single Event Effects observed in all devices 11% = FALSE DUMP 88% INCONSISTENT MONITOR 3 x 10 -13 Glitches per device, per >20 Me. V Hadron 77 Grays Total Dose then 1 oo 4 boards developed short-circuit benjamin. todd@cern. ch

Impact for TE/MPE/MI Power Interlock Controllers XC 95144 x 36 This is not a critical part, it works in parallel to the Programmable Logic Controller (move already prepared away from UJ 56, UJ 14 and UJ 16) Beam Interlock System XC 95288 x 300 not a critical part, it provides monitor data to the Beam Interlock Controller XC 95288 XL x 34 Needs two to be effected simultaneously to be critical, even so: requested move away from UJ 56 (DIF/DIC) TZ 76/UA 63/UA 67 now shielded BIC will not be in a ‘critical’ area 77 Gy = many 10’s of years of LHC operation Working on contingencies – shorter turn around to replace affected HW benjamin. todd@cern. ch

In reality… XC 9500 XL - 3. 3 V - 350 nm assume Cross-Section 1 x 10 -10 Per >20 Me. V Hadron assume UA = 1 x 107 >20 Me. V Hadrons per year (0. 01 Gy/y) For all (34) devices, MTBSEU ≈ 30 years ≈ once in LHC lifetime, FALSE BEAM DUMP ≈ 10% chance in LHC lifetime that REDUNDANCY is LOST for one mission Same order of magnitude as ‘normal’ electrical failure of CPLD (Xilinx Documents) XC 9500 - 5 V - 500 nm assume Cross-Section 1 x 10 -12 Per >20 Me. V Hadron assume RR = 1 x 109 >20 Me. V Hadrons per year (1 Gy/y) For all (336) devices, MTBSEU ≈ 3 years ≈ 6 -7 INCONSISTENT MONITOR DATA READINGS in LHC lifetime (BIS+PIC), ≈ 10% chance of FALSE DUMP in LHC lifetime (PIC), Same order of magnitude as ‘normal’ electrical failure of CPLD (Xilinx Documents) benjamin. todd@cern. ch

Prior to movements this year… CIBU : User Interface Locations IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 IR 8 other SR 1 SR 2 SR 3 SR 4 SR 5 SR 6 SR 7 UA 83 CCR US 151 UA 23 UJ 33 UA 43 UJ 56 UA 63 UJ 76 UA 87 USA 151 UA 27 UA 47 USC 55 UA 67 TZ 76 UX 85 USA 152 SX 4 RR 53 US 65 RR 73 US 851 RR 13 CR 4 RR 57 US 651 RR 77 RR 17 US 451 UJ 14 UJ 16 “critical areas” BIC : Beam Interlock Controller Locations IR 1 IR 2 IR 3 IR 4 IR 5 US 15 IR 6 IR 7 IR 8 other CCC SR 2 SR 3 UA 43 UJ 56 UA 63 SR 7 SR 8 UA 23 UJ 33 UA 47 UCS 55 UA 67 TZ 76 UA 83 UA 27 UA 87 benjamin. todd@cern. ch

Prior to movements this year… PIC : Powering Interlock Controller – PLC Locations IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 UJ 14 UA 23 UJ 16 UA 27 UJ 33 UA 43 UJ 56 UA 63 UA 47 UCS 55 UA 67 IR 8 TZ 76 UA 83 UA 87 PIC : Powering Interlock Controller – XC 95144 Locations IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 RR 13 UA 23 UJ 14 UA 27 UJ 33 IR 8 UA 43 RR 53 UA 63 RR 73 UA 83 UA 47 UJ 56 UA 67 RR 77 UA 87 UJ 16 UCS 55 RR 17 RR 57 “critical areas” benjamin. todd@cern. ch

FIN benjamin. todd@cern. ch