XC 9500 XL New 3 3 v ISP

XC 9500 XL Key Features w High performance l t. PD = 4 ns,

XC 9500 XL Architecture Embraces In-System Changes w Advanced, 2 nd Generation Pin. Locking

XC 9500 XL System Features w I/O Flexibility l 5 v tolerant; direct interface

New XC 9500 XL 3. 3 V Family Macrocells XC 9536 X XC 9572

Most Complete JTAG Testability w IEEE Std 1149. 1 boundary-scan l l testability &

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer Uses standard IR

Productive Implementation Flow for CPLDs w Simplified Project Management w Implementation Templates for Speed

Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY STREAM-LINED OPERATIONS ù 1

XC 9500 XL The Complete CPLD Solution w Product Life Cycle Support w Flexible

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XC 9500 XL New 3. 3 v ISP CPLDs

XC 9500 XL Key Features w High performance l t. PD = 4 ns, f. SYS = 200 MHz w 36 to 288 macrocell densities w Highest programming reliability l 10, 000 program/erase cycles w Most complete IEEE 1149. 1 JTAG support w Space-efficient packaging, including chip scale pkg w Industry’s first 0. 35 um Flash CPLD

XC 9500 XL Architecture Embraces In-System Changes w Advanced, 2 nd Generation Pin. Locking l Superior routability with speed w Maximum Flexibility l l l 54 -input function block fan-in 90 p-terms per output 3 global, locally invertible clocks global set/reset pin p-term OE per macrocell clock enable

XC 9500 XL System Features w I/O Flexibility l 5 v tolerant; direct interface to 3. 3 v & 2. 5 v w Input hysteresis on all pins w User programmable grounds w Bus hold circuitry for simple bus interface w Easy ATE integration for ISP & JTAG l fast, concurrent programming times

New XC 9500 XL 3. 3 V Family Macrocells XC 9536 X XC 9572 XLXC 95144 XLXC 95288 XL L 288 36 72 144 800 1600 3200 6400 t. PD (ns) 4 5 5 6 f. SYSTEM 200 178 151 Usable Gates Packages (Max. User I/Os) BGA CSP 44 PC (34) 64 VQ (36) 64 VQ(52) 100 TQ (72)100 TQ (81) 144 TQ (117) 208 PQ (168) 48 CS (36) 48 CS (38)144 CS (117) 352 BG (192)

Most Complete JTAG Testability w IEEE Std 1149. 1 boundary-scan l l testability & advanced system debug/diagnosis 8 instructions supported (incl. CLAMP) w Full support on all family members w Industry-standard ISP interface w Complete 3 rd party support

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer Uses standard IR techniques for mounting to PC board New 48 -pin CSP: 1/3 size of the VQ 44

Productive Implementation Flow for CPLDs w Simplified Project Management w Implementation Templates for Speed & Density w Push Button Design Flows USER BENEFITS w Faster Clock Speeds w Higher Device Utilization l optimized logic/cm 2 w Industry’s Best Pin. Locking l more design flexibility, less

Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY STREAM-LINED OPERATIONS ù 1 st with Flash ISPù Stream-lined ù Only true 0. 35 um device/pkg ù Apply memory offerings R&D advantagesù High volume packages to CPLDs ù 10 ns slowest speed ù Long-term foundry grade agreements “MEMORY STYLE” MANUFACTURING ù Off-shore sort, test and assembly ù Multi-site parallel test ù Fast time-to-market

XC 9500 XL The Complete CPLD Solution w Product Life Cycle Support w Flexible 3. 3 v ISP Architecture w New Leadership Features w Productive Software w Lowest Cost Solution