XC 9500 Architectural Features XC 9500 Architectural Features

XC 9500 Architectural Features ®

XC 9500 Architectural Features w Predictable, all pins fast, PAL-like architecture w Fast. CONNECT switch matrix provides 100% routing with very high device utilization w Flexible function block — 36 inputs with 18 outputs — Product term expansion with up to 90 product terms per macrocell — Global and product term clocks — Global and product term output enables — Global and product term set/reset signals ® www. xilinx. com

XC 9500 Architecture 3 JTAG Port JTAG Controller In-System Programming Controller Function Block 1 I/O Function Block 2 I/O I/O - Global Clocks I/O - Global Set/Reset I/O - Global Tri-States Blocks Fast. CONNECT Switch Matrix Function Block 3 3 1 Function Block n 2 or 4 ® www. xilinx. com

XC 9500 Function Block w Flexible “ 36 V 18” PAL Blocks ® www. xilinx. com

Fast. CONNECTTM Switch Matrix w 100% routable, high-speed connections ® www. xilinx. com

XC 9500 Macrocell w Powerful, flexible macrocell logic: — 1 to 90 p-terms — Individual p-term or global signals for clock, OE, set, reset ® www. xilinx. com

XC 9500 P-Term Allocation Example #1 ® www. xilinx. com

Complex P-Term Allocation Example #2 ® www. xilinx. com

XC 9500 P-Term Allocator Logic w Flexible, bi-directional cascade / bypass capability ® www. xilinx. com

XC 9500 Clock, Set/Reset Capability ® www. xilinx. com

XC 9500 OE Capability ® www. xilinx. com

XC 9500 Power-Up Characteristics VCCINT 3. 8 V (Typ) 0 V No Quiescent Power State User Operation Quiescent No State Power Initialization of User Registers w Well-behaved quiescent characteristics: —JTAG, I/O pins, internal operation disabled — 10 kohm pull-up resistors activated on each user I/O pin ® www. xilinx. com