X 86 Assembly Data II 1 Intel x

X 86 Assembly - Data II: 1

Intel x 86 Processors ¢ Totally dominate computer market ¢ Evolutionary design § Backwards compatible up until 8086, introduced in 1978 § Added more features as time goes on ¢ Complex instruction set computer (CISC) § Many different instructions with many different formats But, only small subset encountered with Linux programs § Hard to match performance of Reduced Instruction Set Computers (RISC) § But, Intel has done just that! § II: 2

Intel x 86 Evolution: Milestones Name ¢ 8086 Date 1978 Transistors 29 K MHz 5 -10 § First 16 -bit processor. Basis for IBM PC & DOS § 1 MB address space ¢ 386 § § ¢ 1985 275 K 16 -33 First 32 bit processor , referred to as IA 32 Added “flat addressing” Capable of running Unix 32 -bit Linux/gcc uses no instructions introduced in later models Pentium 4 F 2005 230 M 2800 -3800 § First 64 -bit processor § Meanwhile, Pentium 4 s (Netburst arch. ) phased out in favor of “Core” line II: 3

Intel x 86 Processors: Overview Architectures X 86 -16 Processors 8086 286 X 86 -32/IA 32 MMX 386 486 Pentium MMX SSE Pentium III SSE 2 Pentium 4 SSE 3 Pentium 4 E X 86 -64 / EM 64 t Pentium 4 F SSE 4 Core 2 Duo Core i 7 time IA: often redefined as latest Intel architecture II: 4

Intel x 86 Processors, contd. ¢ Machine Evolution § § § § ¢ 486 Pentium/MMX Pentium. Pro Pentium III Pentium 4 Core 2 Duo 1989 1993 1997 1995 1999 2001 2006 1. 9 M 3. 1 M 4. 5 M 6. 5 M 8. 2 M 42 M 291 M Added Features § Instructions to support multimedia operations Parallel operations on 1, 2, and 4 -byte data, both integer & FP § Instructions to enable more efficient conditional operations § ¢ Linux/GCC Evolution § Very limited II: 5

New Species: IA 64 / Itanium / IPF Name ¢ Itanium Date 2001 Transistors 10 M § First shot at 64 -bit architecture: first called IA 64 § Radically new instruction set designed for high performance § Can run existing IA 32 programs On-board “x 86 engine” § Joint project with Hewlett-Packard § ¢ Itanium 2 2002 221 M § Big performance boost Itanium 2 Dual-Core 2006 1. 7 B ¢ Itanium has not taken off in marketplace ¢ § Lack of backward compatibility, no good compiler support, Pentium 4 got too good II: 6

x 86 Clones: Advanced Micro Devices (AMD) ¢ Historically § AMD has followed just behind Intel § A little bit slower, a lot cheaper ¢ Then § Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies § Built Opteron: tough competitor to Pentium 4 § Developed x 86 -64, their own 64 -bit extension ¢ Recently § Intel much quicker with dual core design § Intel currently ahead in performance § Intel’s EM 64 T backwards compatible to x 86 -64 II: 7

Intel’s 64 -Bit ¢ Intel Attempted Radical Shift from IA 32 to IA 64 § Totally different architecture (Itanium) § Executes IA 32 code only as legacy § Performance disappointing ¢ AMD Stepped in with Evolutionary Solution § x 86 -64 (now called “AMD 64”) ¢ Intel Felt Obligated to Focus on IA 64 § Hard to admit mistake or that AMD is better ¢ 2004: Intel Announces EM 64 T extension to IA 32 § Extended Memory 64 -bit Technology § Almost identical to x 86 -64! ¢ Meanwhile: EM 64 t well introduced, however, still often not used by OS, programs II: 8

Our Coverage ¢ IA 32 (through Section 3. 12) § The traditional x 86 ¢ x 86 -64/EM 64 T (Section 3. 13) § The emerging standard II: 9

Definitions ¢ ¢ Architecture: (also instruction set architecture: ISA) The parts of a processor design that one needs to understand to write assembly code. Microarchitecture: Implementation of the architecture. ¢ Architecture examples: instruction set specification, registers. Microarchitecture examples: cache sizes, core frequency. ¢ Example ISAs (Intel): x 86, IA, Itanium ¢ II: 10

Assembly Programmer’s View CPU PC Registers Condition Codes ¢ Memory Addresses Data Instructions Object Code Program Data OS Data Stack Programmer-Visible State § PC: Program counter Address of next instruction § Called “EIP” (IA 32) § § Register file § Heavily used program data § Condition codes Store status information about most recent arithmetic operation § Used for conditional branching § § Memory Byte addressable array § Code, user data, (some) OS data § Includes stack used to support procedures § II: 11

general purpose Integer Registers (IA 32) Origin (mostly obsolete) %eax %ah %al accumulate %ecx %ch %cl counter %edx %dh %dl data %ebx %bh %bl base %esi %si source index %edi %di destination index %sp stack pointer %bp base pointer %esp %ebp II: 12

Instruction Syntax ¢ Intel/Microsoft § Op, Dest/Src, Src simple: push ebp mov ebp, esp mov edx, DWORD PTR [ebp+8] mov eax, DWORD PTR [ebp+12] add eax, DWORD PTR [edx] mov DWORD PTR [edx], eax pop ebp ret ¢ AT&T/Linux/Gnu § Op, Src, Dest/Src simple: pushl movl addl movl popl ret int simple(int *xp, int y) { int t = *xp + y; *xp = t; return t; } %ebp %esp, %ebp 8(%ebp), %edx 12(%ebp), %eax (%edx), %eax, (%edx) %ebp II: 13

Turning C into Object Code § Code in files p 1. c p 2. c § Compile with command: gcc -O p 1. c p 2. c -o p Use optimizations (-O) § Put resulting binary in file p § text C program (p 1. c p 2. c) Compiler (gcc -S) text ASM program (p 1. s p 2. s) Assembler (gcc or as) binary Object program (p 1. o p 2. o) Linker (gcc or ld) binary Static libraries (. a) Executable program (p) II: 14

Compiling Into Assembly C Code int sum(int x, int y) { int t = x+y; return t; } Generated IA 32 Assembly sum: pushl %ebp movl %esp, %ebp movl 12(%ebp), %eax addl 8(%ebp), %eax movl %ebp, %esp popl %ebp ret Obtain with command gcc -O -S code. c Some compilers use single instruction “leave” Produces file code. s II: 15

Assembly Characteristics: Data Types ¢ “Integer” data of 1, 2, or 4 bytes § Data values § Addresses (untyped pointers) ¢ Floating point data of 4, 8, or 10 bytes ¢ No aggregate types such as arrays or structures § Just contiguously allocated bytes in memory II: 16

Assembly Characteristics: Operations ¢ Perform arithmetic function on register or memory data ¢ Transfer data between memory and register § Load data from memory into register § Store register data into memory ¢ Transfer control § Unconditional jumps to/from procedures § Conditional branches II: 17

Object Code for sum 0 x 401040 0 x 55 0 x 89 0 xe 5 0 x 8 b 0 x 45 0 x 0 c 0 x 03 0 x 45 0 x 08 0 x 89 0 xec 0 x 5 d 0 xc 3 <sum>: ¢ sum: pushl %ebp movl %esp, %ebp movl 12(%ebp), %eax addl 8(%ebp), %eax movl %ebp, %esp popl %ebp ret ¢ • Total of 13 bytes • Each instruction 1, 2, or 3 bytes • Starts at address 0 x 401040 Assembler § § Translates. s into. o Binary encoding of each instruction Nearly-complete image of executable code Missing linkages between code in different files Linker § Resolves references between files § Combines with static run-time libraries E. g. , code for malloc, printf § Some libraries are dynamically linked § Linking occurs when program begins execution § II: 18

Machine Instruction Example ¢ int t = x+y; § Add two signed integers ¢ “Long” words in GCC parlance § Same instruction whether signed or unsigned § Operands: x: Register %eax y: Memory M[%ebp+8] t: Register %eax – Return function value in %eax § Similar to expression: x += y More precisely: int eax; int *ebp; eax += ebp[2] 03 45 08 Assembly § Add 2 4 -byte integers addl 8(%ebp), %eax 0 x 401046: C Code ¢ Object Code § 3 -byte instruction § Stored at address 0 x 401046 II: 19

Disassembling Object Code Disassembled 00401040 <_sum>: 0: 55 1: 89 e 5 3: 8 b 45 0 c 6: 03 45 08 9: 89 ec b: 5 d c: c 3 d: 8 d 76 00 ¢ push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Disassembler objdump -d p § Useful tool for examining object code § Analyzes bit pattern of series of instructions § Produces approximate rendition of assembly code § Can be run on either a. out (complete executable) or. o file II: 20

Alternate Disassembly Disassembled Object 0 x 401040: 0 x 55 0 x 89 0 xe 5 0 x 8 b 0 x 45 0 x 0 c 0 x 03 0 x 45 0 x 08 0 x 89 0 xec 0 x 5 d 0 xc 3 0 x 401040 0 x 401041 0 x 401043 0 x 401046 0 x 401049 0 x 40104 b 0 x 40104 c 0 x 40104 d ¢ <sum>: <sum+1>: <sum+3>: <sum+6>: <sum+9>: <sum+11>: <sum+12>: <sum+13>: push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Within gdb Debugger gdb p disassemble sum § Disassemble procedure x/13 b sum § Examine the 13 bytes starting at sum II: 21

What Can be Disassembled? % objdump -d WINWORD. EXE: file format pei-i 386 No symbols in "WINWORD. EXE". Disassembly of section. text: 30001000 <. text>: 30001000: 55 30001001: 8 b ec 30001003: 6 a ff 30001005: 68 90 10 00 30 3000100 a: 68 91 dc 4 c 30 ¢ ¢ push mov push %ebp %esp, %ebp $0 xffff $0 x 30001090 $0 x 304 cdc 91 Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source II: 22

general purpose Integer Registers (IA 32) Origin (mostly obsolete) %eax %ah %al accumulate %ecx %ch %cl counter %edx %dh %dl data %ebx %bh %bl base %esi %si source index %edi %di destination index %sp stack pointer %bp base pointer %esp %ebp II: 23

Moving Data: IA 32 ¢ Moving Data § movx Source, Dest § x in {b, w, l} § movl Source, Dest: Move 4 -byte “long word” § movw Source, Dest: Move 2 -byte “word” § movb Source, Dest: Move 1 -byte “byte” ¢ %eax %ecx %edx %ebx %esi %edi %esp %ebp Lots of these in typical code II: 24

Moving Data: IA 32 ¢ Moving Data movl Source, Dest: ¢ Operand Types § Immediate: Constant integer data %eax %ecx %edx %ebx %esi Example: $0 x 400, $-533 %edi § Like C constant, but prefixed with ‘$’ %esp § Encoded with 1, 2, or 4 bytes %ebp § Register: One of 8 integer registers § Example: %eax, %edx § But %esp and %ebp reserved for special use § Others have special uses for particular instructions § Memory: 4 consecutive bytes of memory at address given by register § Simplest example: (%eax) § Various other “address modes” § II: 25

movl Operand Combinations Source movl Dest Src, Dest C Analog Imm Reg movl $0 x 4, %eax Mem movl $-147, (%eax) temp = 0 x 4; Reg movl %eax, %edx Mem movl %eax, (%edx) temp 2 = temp 1; Mem Reg temp = *p; movl (%eax), %edx *p = -147; *p = temp; Cannot do memory-memory transfer with a single instruction II: 26

Simple Memory Addressing Modes ¢ Normal (R) Mem[Reg[R]] § Register R specifies memory address movl (%ecx), %eax ¢ Displacement D(R) Mem[Reg[R]+D] § Register R specifies start of memory region § Constant displacement D specifies offset movl 8(%ebp), %edx II: 27

Using Simple Addressing Modes int main(. . . ) { int x = 3; int y = 5; swap(&x, &y); return 1; } void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } swap: pushl %ebp movl %esp, %ebp pushl %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) movl -4(%ebp), %ebx movl %ebp, %esp popl %ebp ret Set Up Body Finish II: 28

Using Simple Addressing Modes void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } swap: pushl %ebp movl %esp, %ebp pushl %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) movl -4(%ebp), %ebx movl %ebp, %esp popl %ebp ret Set Up Body Finish II: 29

Understanding Swap void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } • • • Offset 12 yp 8 xp 4 Rtn adr Stack (in memory) 0 Old %ebp Register %ecx %edx %eax %ebx Value yp xp t 1 t 0 %ebp -4 Old %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = yp xp *yp (t 1) *xp (t 0) eax ebx II: 30

Understanding Swap 123 Address 0 x 124 456 0 x 120 0 x 11 c %eax Offset %edx %ecx %ebx %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 31

Understanding Swap 123 Address 0 x 124 456 0 x 120 0 x 11 c %eax Offset %edx %ecx 0 x 120 %ebx %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 32

Understanding Swap 123 Address 0 x 124 456 0 x 120 0 x 11 c %eax %edx 0 x 124 %ecx 0 x 120 Offset %ebx %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 33

Understanding Swap 123 Address 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 Offset %ebx %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 34

Understanding Swap 123 Address 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx Offset 123 %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 35

Understanding Swap 456 Address 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx Offset 123 %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 36

Understanding Swap 456 Address 0 x 124 123 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx Offset 123 %esi 0 x 114 yp 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 %ebp %edi 0 x 104 -4 %esp %ebp 0 x 118 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = 0 x 100 yp xp *yp (t 1) *xp (t 0) eax ebx II: 37

Complete Memory Addressing Modes ¢ Most General Form D(Rb, Ri, S) Mem[Reg[Rb]+S*Reg[Ri]+ D] § D: § Rb: § Ri: Constant “displacement” 1, 2, or 4 bytes Base register: Any of 8 integer registers Index register: Any, except for %esp § Unlikely you’d use %ebp, either § S: Scale: 1, 2, 4, or 8 (why these numbers? ) ¢ Special Cases (Rb, Ri) D(Rb, Ri) (Rb, Ri, S) Mem[Reg[Rb]+Reg[Ri]] Mem[Reg[Rb]+Reg[Ri]+D] Mem[Reg[Rb]+S*Reg[Ri]] II: 38

Address Computation Examples %edx 0 xf 000 %ecx 0 x 100 Expression Address Computation Address 0 x 8(%edx) (%edx, %ecx, 4) 0 x 80(, %edx, 2) II: 39

Address Computation Examples %edx 0 xf 000 %ecx 0 x 100 Expression Address Computation Address 0 x 8(%edx) 0 xf 000 + 0 x 8 0 xf 008 (%edx, %ecx) 0 xf 000 + 0 x 100 0 xf 100 (%edx, %ecx, 4) 0 xf 000 + 4*0 x 100 0 xf 400 0 x 80(, %edx, 2) 2*0 xf 000 + 0 x 80 0 x 1 e 080 II: 40

Address Computation Instruction ¢ ¢ leal Src, Dest § Src is address mode expression § Set Dest to address denoted by expression Uses § Computing addresses without a memory reference § E. g. , translation of p = &x[i]; § Computing arithmetic expressions of the form x + k*y § k = 1, 2, 4, or 8 II: 42

Some Arithmetic Operations ¢ Two Operand Instructions: Format addl Src, Dest Computation Dest = Dest + Src subl Src, Dest = Dest - Src imull Src, Dest = Dest * Src sall Src, Dest = Dest << Src Also called shll sarl Src, Dest = Dest >> Src Arithmetic shrl Src, Dest = Dest >> Src Logical xorl Src, Dest = Dest ^ Src andl Src, Dest = Dest & Src, Dest = Dest | Src orl ¢ No distinction between signed and unsigned int (why? ) II: 43

Some Arithmetic Operations ¢ ¢ One Operand Instructions incl Dest = Dest + 1 decl Dest = Dest - 1 negl Dest = -Dest notl Dest = ~Dest See book for more instructions II: 44

Using leal for Arithmetic Expressions int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } arith: pushl %ebp movl %esp, %ebp movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax movl %ebp, %esp popl %ebp ret Set Up Body Finish II: 45

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax • • • Offset 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp # # # # eax edx ecx eax = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp II: 46

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax • • • Offset 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp # # # # eax edx ecx eax = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp II: 47

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax • • • Offset 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp # # # # eax edx ecx eax = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp II: 48

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax • • • Offset 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp # # # # eax edx ecx eax = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp II: 49

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax movl %ebp, %esp popl %ebp ret # # eax eax = = Set Up Body Finish x x^y t 1>>17 t 2 & 8185 II: 50

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax movl %ebp, %esp popl %ebp ret # # eax eax = = Set Up Body Finish x x^y (t 1) t 1>>17 (t 2) t 2 & 8185 II: 51

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax movl %ebp, %esp popl %ebp ret # # eax eax = = Set Up Body Finish x x^y (t 1) t 1>>17 (t 2) t 2 & 8185 II: 52

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl movl %ebp, %esp popl %ebp ret 213 = 8192, 213 – 7 = 8185 movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax # # eax eax = = Set Up Body Finish x x^y (t 1) t 1>>17 (t 2) t 2 & 8185 II: 53