William Stallings Computer Organization and Architecture Chapter 6

William Stallings Computer Organization and Architecture Chapter 6 Input/Output 1

Input/Output Problems z Wide variety of peripherals y. Delivering different amounts of data y. At different speeds y. In different formats z All slower than CPU and RAM z Need I/O modules 2

Input/Output Module z Interface to CPU and Memory z Interface to one or more peripherals z GENERIC MODEL OF I/O DIAGRAM 6. 1 3

External Devices z Human readable y. Screen, printer, keyboard z Machine readable y. Monitoring and control z Communication y. Modem y. Network Interface Card (NIC) 4

I/O Module Function z Control & Timing z CPU Communication z Device Communication z Data Buffering z Error Detection 5

I/O Steps z CPU checks I/O module device status z I/O module returns status z If ready, CPU requests data transfer z I/O module gets data from device z I/O module transfers data to CPU z Variations for output, DMA, etc. 6

I/O Module Diagram Systems Bus Interface Data Lines Address Lines Data Lines External Device Interface Data Register Status/Control Register Input Output Logic External Device Interface Logic Data Status Control 7

I/O Module Decisions z Hide or reveal device properties to CPU z Support multiple or single device z Control device functions or leave for CPU z Also O/S decisions ye. g. Unix treats everything it can as a file 8

Input Output Techniques z Programmed z Interrupt driven z Direct Memory Access (DMA) 9

Programmed I/O z CPU has direct control over I/O y. Sensing status y. Read/write commands y. Transferring data z CPU waits for I/O module to complete operation z Wastes CPU time 10

Programmed I/O - detail z CPU requests I/O operation z I/O module performs operation z I/O module sets status bits z CPU checks status bits periodically z I/O module does not inform CPU directly z I/O module does not interrupt CPU z CPU may wait or come back later 11

I/O Commands z CPU issues address y. Identifies module (& device if >1 per module) z CPU issues command y. Control - telling module what to do xe. g. spin up disk y. Test - check status xe. g. power? Error? y. Read/Write x. Module transfers data via buffer from/to device 12

Addressing I/O Devices z Under programmed I/O data transfer is very like memory access (CPU viewpoint) z Each device given unique identifier z CPU commands contain identifier (address) 13

I/O Mapping z Memory mapped I/O y Devices and memory share an address space y I/O looks just like memory read/write y No special commands for I/O x. Large selection of memory access commands available z Isolated I/O y Separate address spaces y Need I/O or memory select lines y Special commands for I/O x. Limited set 14

Interrupt Driven I/O z Overcomes CPU waiting z No repeated CPU checking of device z I/O module interrupts when ready 15

Interrupt Driven I/O Basic Operation z CPU issues read command z I/O module gets data from peripheral whilst CPU does other work z I/O module interrupts CPU z CPU requests data z I/O module transfers data 16

CPU Viewpoint z Issue read command z Do other work z Check for interrupt at end of each instruction cycle z If interrupted: y. Save context (registers) y. Process interrupt x. Fetch data & store z See Operating Systems notes 17

Design Issues z How do you identify the module issuing the interrupt? z How do you deal with multiple interrupts? yi. e. an interrupt handler being interrupted 18

Identifying Interrupting Module (1) z Different line for each module y. PC y. Limits number of devices z Software poll y. CPU asks each module in turn y. Slow 19

Identifying Interrupting Module (2) z Daisy Chain or Hardware poll y. Interrupt Acknowledge sent down a chain y. Module responsible places vector on bus y. CPU uses vector to identify handler routine z Bus Master y. Module must claim the bus before it can raise interrupt ye. g. PCI & SCSI 20

Multiple Interrupts z Each interrupt line has a priority z Higher priority lines can interrupt lower priority lines z If bus mastering only current master can interrupt 21

Example - PC Bus z 80 x 86 has one interrupt line z 8086 based systems use one 8259 A interrupt controller z 8259 A has 8 interrupt lines 22

Sequence of Events z 8259 A accepts interrupts z 8259 A determines priority z 8259 A signals 8086 (raises INTR line) z CPU Acknowledges z 8259 A puts correct vector on data bus z CPU processes interrupt 23

PC Interrupt Layout 8259 A IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 8086 INTR 24

ISA Bus Interrupt System z ISA bus chains two 8259 As together z Link is via interrupt 2 z Gives 15 lines y 16 lines less one for link z IRQ 9 is used to re-route anything trying to use IRQ 2 y. Backwards compatibility z Incorporated in chip set 25

ISA Interrupt Layout (IRQ 2) 8259 A IRQ 0 (8) IRQ 1 (9) IRQ 2 (10) IRQ 3 (11) IRQ 4 (12) IRQ 5 (13) IRQ 6 (14) IRQ 7 (15) 8259 A IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 80 x 86 INTR 26

Foreground Reading z http: //www. pcguide. com/ref/mbsys/res/irq/func. htm z In fact look at http: //www. pcguide. com/ 27

Direct Memory Access z Interrupt driven and programmed I/O require active CPU intervention y. Transfer rate is limited y. CPU is tied up z DMA is the answer 28

DMA Function z Additional Module (hardware) on bus z DMA controller takes over from CPU for I/O 29

DMA Operation z CPU tells DMA controller: y. Read/Write y. Device address y. Starting address of memory block for data y. Amount of data to be transferred z CPU carries on with other work z DMA controller deals with transfer z DMA controller sends interrupt when finished 30

DMA Transfer Cycle Stealing z DMA controller takes over bus for a cycle z Transfer of one word of data z Not an interrupt y. CPU does not switch context z CPU suspended just before it accesses bus yi. e. before an operand or data fetch or a data write z Slows down CPU but not as much as CPU doing transfer 31

Aside z What effect does caching memory have on DMA? z Hint: how much are the system buses available? 32

DMA Configurations (1) CPU DMA Controller I/O Device Main Memory z Single Bus, Detached DMA controller z Each transfer uses bus twice y I/O to DMA then DMA to memory z CPU is suspended twice 33

DMA Configurations (2) CPU DMA Controller I/O Device DMA Controller Main Memory I/O Device z Single Bus, Integrated DMA controller z Controller may support >1 device z Each transfer uses bus once y. DMA to memory z CPU is suspended once 34

DMA Configurations (3) DMA Controller CPU I/O Device z Separate I/O Bus z Bus supports all DMA enabled devices z Each transfer uses bus once Main Memory I/O Device y. DMA to memory z CPU is suspended once 35

I/O Channels z I/O devices getting more sophisticated z e. g. 3 D graphics cards z CPU instructs I/O controller to do transfer z I/O controller does entire transfer z Improves speed y. Takes load off CPU y. Dedicated processor is faster 36

Interfacing z Connecting devices together z Bit of wire? z Dedicated processor/memory/buses? z E. g. SCSI, Fire. Wire 37

Small Computer Systems Interface (SCSI) z Parallel interface z 8, 16, 32 bit data lines z Daisy chained z Devices are independent z Devices can communicate with each other as well as host 38

SCSI - 1 z Early 1980 s z 8 bit z 5 MHz z Data rate 5 MBytes. s-1 z Seven devices y. Eight including host interface 39

SCSI - 2 z 1991 z 16 and 32 bit z 10 MHz z Data rate 20 or 40 Mbytes. s-1 z (Check out Ultra/Wide SCSI) 40

SCSI Signaling (1) z Between initiator and target y. Usually host & device z Bus free? (c. f. Ethernet) z Arbitration - take control of bus (c. f. PCI) z Select target z Reselection y. Allows reconnection after suspension ye. g. if request takes time to execute, bus can be released 41

SCSI Signaling (2) z Command - target requesting from initiator z Data request z Status request z Message request (both ways) 42

SCSI Bus Phases Reset Bus free Arbitration (Re)Selection Command, Data, Status, Message 43

SCSI Timing Diagram 44

Configuring SCSI z Bus must be terminated at each end y. Usually one end is host adapter y. Plug in terminator or switch(es) z SCSI Id must be set y. Jumpers or switches y. Unique on chain y 0 (zero) for boot device y. Higher number is higher priority in arbitration 45

IEEE 1394 Fire. Wire z High performance serial bus z Fast z Low cost z Easy to implement z Also being used in digital cameras, VCRs and TV 46

Fire. Wire Configuration z Daisy chain z Up to 63 devices on single port y. Really 64 of which one is the interface itself z Up to 1022 buses can be connected with bridges z Automatic configuration z No bus terminators z May be tree structure 47

Fire. Wire 3 Layer Stack z Physical y. Transmission medium, electrical and signaling characteristics z Link y. Transmission of data in packets z Transaction y. Request-response protocol 48

Fire. Wire - Physical Layer z Data rates from 25 to 400 Mbps z Two forms of arbitration y. Based on tree structure y. Root acts as arbiter y. First come first served y. Natural priority controls simultaneous requests xi. e. who is nearest to root y. Fair arbitration y. Urgent arbitration 49

Fire. Wire - Link Layer z Two transmission types y. Asynchronous x. Variable amount of data and several bytes of transaction data transferred as a packet x. To explicit address x. Acknowledgement returned y. Isochronous x. Variable amount of data in sequence of fixed size packets at regular intervals x. Simplified addressing x. No acknowledgement 50

Foreground Reading z Check out Universal Serial Bus (USB) z Compare with other communication standards e. g. Ethernet 51

Gambar SCSI 52

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TUGAS 01 z PERBEDAAN : z SCSI vs USB z SCSI vs Firewire z USB vs Firewire 54