William Stallings Computer Organization and Architecture Chapter 17

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William Stallings Computer Organization and Architecture Chapter 17 Micro-programmed Control Rev. (2008 -09) by

William Stallings Computer Organization and Architecture Chapter 17 Micro-programmed Control Rev. (2008 -09) by Luciano Gualà 15 - 1

Hardwired vs Micro-programmed Control • Hardwired implementation of the CU § synthesizing a sequential

Hardwired vs Micro-programmed Control • Hardwired implementation of the CU § synthesizing a sequential circuit to obtain the desidered input-output relations for control signals • Micro-programmed implementation of the CU § use sequences of micro-instructions to implement the execution of CPU micro-operations • Called micro-programming or firmware production, since each sequence is made up by a small number of very simple operations Rev. (2008 -09) by Luciano Gualà 15 - 2

Implementation (1) • For each micro-operation (m. OP) all the control unit does is

Implementation (1) • For each micro-operation (m. OP) all the control unit does is to generate a set of control signals • Each control signal is on or off • Represent each control signal by a bit • The set of control bits is a control word (CW) • Each m. OP corresponds to a different CW • Each m. OP is executed during one execution cycle of the CU, which starts by reading the current CW to be executed and ends by preparing the address of the next CW to be executed Rev. (2008 -09) by Luciano Gualà 15 - 3

Implementation (2) • Example of CWs for the m. OPs corresponding to instruction fetch

Implementation (2) • Example of CWs for the m. OPs corresponding to instruction fetch t 1 : t 2 : MAR <- (PC) MBR <- (memory) ALU <- (PC) + 1 t 3: IR <- (MBR) AC <- (ALU) t 4: PC <- (AC) CW 1 C 2 C 5, C 0, CR C 14, CA 1, …, CAk C 4 CW 3 C 9 C 15 CW 4 CW 2 • Add to each CW address information to specify the next m. OP, depending on some conditions Rev. (2008 -09) by Luciano Gualà 15 - 4

Implementation (3) • Have a sequence of CW for each CPU instruction or substep

Implementation (3) • Have a sequence of CW for each CPU instruction or substep of it (micro-procedure) • Each micro-procedure is terminated by a (possibly conditional) jump to another micro-procedure CW Cond. Next m. OP • All CWs are put in a memory, called Control Memory, which can now be used to drive the CU behavior • All is needed is to define the flow of execution of CWs, i. e. the sequence of addresses in the control memory whose corresponding CWs have to be activated Rev. (2008 -09) by Luciano Gualà 15 - 5

Instruction fetch t 1 : t 2 : MAR <- (PC) MBR <- (memory)

Instruction fetch t 1 : t 2 : MAR <- (PC) MBR <- (memory) ALU <- (PC) + 1 t 3: IR <- (MBR) AC <- (ALU) t 4: PC <- (AC) t 5 : t 6 : C 2 C 5, C 0, CR C 14, CA 1, …, CAk C 4 C 9 C 15 OF: direct addressing MAR <- (IRaddress) C 16 MBR <- (memory) C 0, C 5, CR Interrupt t 1 : t 2 : MAR <- (MBR) C 16 MBR <- (memory) C 0, C 5, CR OF: indirect addressing t 2 : t 3 : t 4 : t 5 : MBR <- (PC) C 1 MAR <- (SP) Memory <- (MBR) C 12, C 0, CW MAR <- Interrupt-code MBR <- (Memory) C 5, C 0, CR PC <- (MBR) C 3 Rev. (2008 -09) by Luciano Gualà 15 - 6

Implementation (4) curr. CW CW 1 CW 2 CW 3 CW 4 m. OPs

Implementation (4) curr. CW CW 1 CW 2 CW 3 CW 4 m. OPs C 2 C 5 C 0 CR C 14 CA 1 … CAk C 4 C 9 C 15 Jump False True Next CW CW 7 • Assuming that after fetch the execute phase starts and its first control word is CW 7 • When the jump condition is false the next CW in the sequence is executed Rev. (2008 -09) by Luciano Gualà 15 - 7

Control Memory Fetch cycle routine Indirect Cycle routine Interrupt cycle routine Execute cycle start

Control Memory Fetch cycle routine Indirect Cycle routine Interrupt cycle routine Execute cycle start AND routine ADD routine. . . Jump to Indirect or Execute. . . Jump to Fetch. . . Jump to Op code routine. . . Jump to Fetch or Interrupt Rev. (2008 -09) by Luciano Gualà 15 - 8

Horizontal Micro-programming • Wide CW: reserve one bit of the CW for each control

Horizontal Micro-programming • Wide CW: reserve one bit of the CW for each control signal • Many m. OPs can be executed in parallel, but a large space is used Internal CPU Control Signals System Bus Control Signals Next m. OP Address Inform. Jump Conditions Rev. (2008 -09) by Luciano Gualà 15 - 9

Vertical Micro-programming (1) • Notice: not all combinations of the n control signals are

Vertical Micro-programming (1) • Notice: not all combinations of the n control signals are feasible • Q: number of feasible combinations § Q<2 n • Idea: We can use just log 2 Q bits to encode a combination • Drawbacks: § it requires a complex and therefore slow control logic module § it is difficult to program • Idea: § More bits than strictly necessary are used to encode the possible combinations § Some combinations that are phisically allowable are not possible to encode Rev. (2008 -09) by Luciano Gualà 15 - 10

Vertical Micro-programming (2) • Compromise: § Divide control signals into disjoint groups • Functional

Vertical Micro-programming (2) • Compromise: § Divide control signals into disjoint groups • Functional basis (groups for operand source, addressing mode, …) • Resource basis (groups for ALU, memory, I/O, …) § Criteria • All operations coded within a group cannot be executed in parallel • Any operation in a group can be executed in parallel with any operation in any other group § Implement each group as separate field in memory word § Supports reasonable levels of parallelism without too much complexity § With k groups at most k m. OPs may be executed in parallel Rev. (2008 -09) by Luciano Gualà 15 - 11

Vertical Micro-programming (3) … field decode logic … … control signals Rev. (2008 -09)

Vertical Micro-programming (3) … field decode logic … … control signals Rev. (2008 -09) by Luciano Gualà 15 - 12

Control Unit: core elements • Control Address Register § Contains the address of the

Control Unit: core elements • Control Address Register § Contains the address of the current m. OP in execution and (at the end of each CU execution cycle) of the next m. OP to be executed • Control Buffer Register § Store the content of the current m. OP in execution • Sequencing Logic § Activates reading from the Control Memory of the location at the address in CAR and storing its content in CBR § Decides on the next address to be put in CAR Rev. (2008 -09) by Luciano Gualà 15 - 13

Sequence of operations during each execution cycle of CU (1) 1. Sequencing logic unit

Sequence of operations during each execution cycle of CU (1) 1. Sequencing logic unit issues read command to Control Memory 2. The CW at the address specified in Control Address Register is read into Control Buffer Register 3. CBR content generates control signals to CPU and to system bus, and information used to decide next CW address in the Control Memory Rev. (2008 -09) by Luciano Gualà 15 - 14

Sequence of operations during each execution cycle of CU (2) 4. Sequencing Logic decide

Sequence of operations during each execution cycle of CU (2) 4. Sequencing Logic decide the next CW address based on: § § § jump conditions and next address information in CBR info from IR and from ALU flags current state of the CU, given by the value in CAR 5. then loads the next CW address into the CAR § Next CW address in control memory can be • • Current address + 1 A jump to § § A new micro-procedure within a same CPU instruction A new micro-procedure corresponding to a new CPU instruction Rev. (2008 -09) by Luciano Gualà 15 - 15

Control Unit Organization Control Unit Rev. (2008 -09) by Luciano Gualà 15 - 16

Control Unit Organization Control Unit Rev. (2008 -09) by Luciano Gualà 15 - 16

Organization of the sequencing logic • Sequencing logic decides the address of the next

Organization of the sequencing logic • Sequencing logic decides the address of the next CW to be executed • Its organization depends also on structure of jump conditions and next-m. OP address information in CW § 2 fields containing both addresses needed for the case CU jumps or not (faster but longer CW) § 1 field containing only the address in case of jump, since otherwise CU goes in sequence (needs an adder) § Variable structure of CW: only address information or only control information (much shorter CW but slower execution) Rev. (2008 -09) by Luciano Gualà 15 - 17

Address decoder Control memory CBR Control Address 1 Address 2 … CAR Flags Branch

Address decoder Control memory CBR Control Address 1 Address 2 … CAR Flags Branch Multiplexer logic address selection Rev. (2008 -09) by Luciano IR Gualà 15 - 18

Address decoder Control memory CBR Control … Address field +1 Flags CAR Branch Multiplexer

Address decoder Control memory CBR Control … Address field +1 Flags CAR Branch Multiplexer logic address selection Rev. (2008 -09) by Luciano IR Gualà 15 - 19

Address decoder Control memory CBR Enable Flags Variable Structure CW Branch Entire control field

Address decoder Control memory CBR Enable Flags Variable Structure CW Branch Entire control field Gate and function logic Branch logic Address field +1 CAR Multiplexer Rev. (2008 -09) by Luciano IR Gualà 15 - 20

Hardwired vs Micro-programmed • Micro-programmed control simplifies the design of control unit § Cheaper

Hardwired vs Micro-programmed • Micro-programmed control simplifies the design of control unit § Cheaper § Less error-prone § Much more easier to revise and modify • But the control unit is faster with hardwired CU • Micro-programmed CU is used mainly for CISC architectures since flexibility of CU is more important for a complex instruction set • On the other side, RISC architectures use hardwired CU since with a simpler instruction set flexibility is a less important requirement than speed of execution Rev. (2008 -09) by Luciano Gualà 15 - 21