William Stallings Computer Organization and Architecture 7 th

William Stallings Computer Organization and Architecture 7 th Edition Chapter 5 Internal Memory http: //www. cs. uncc. edu/~abw/ITCS 3182 S 06/index. html 1

Semiconductor Memory Types 2

Semiconductor Memory l RAM n n n Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic 3

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Dynamic RAM l l l l l Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue n Level of charge determines value 5

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DRAM Operation l Address line active when bit read or written n l Transistor switch closed (current flows) Write n Voltage to bit line – High for 1 low for 0 n Then signal address line – Transfers charge to capacitor l Read n Address line selected – transistor turns on n Charge from capacitor fed via bit line to sense amplifier – Compares with reference value to determine 0 or 1 n Capacitor charge must be restored 7

Static RAM l l l l l Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital n Uses flip-flops 8

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Stating RAM Structure 10

Static RAM Operation l l Transistor arrangement gives stable logic state State 1 n n l State 0 n n l l l C 1 high, C 2 low T 1 T 4 off, T 2 T 3 on C 2 high, C 1 low T 2 T 3 off, T 1 T 4 on Address line transistors T 5 T 6 is switch Write – apply value to B & compliment to B Read – value is on line B 11

SRAM vs DRAM l Both volatile n l Dynamic cell n n n l Power needed to preserve data Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static n n Faster Cache 12

Read Only Memory (ROM) l Permanent storage n l l Nonvolatile Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables 13

Types of ROM l Written during manufacture n l Programmable (once) n n l Very expensive for small runs PROM Needs special equipment to program Read “mostly” n Erasable Programmable (EPROM) – Erased by UV n Electrically Erasable (EEPROM) – Takes much longer to write than read n Flash memory – Erase whole memory electrically 14

Organisation in detail l A 16 Mbit chip can be organised as 1 M of 16 bit words A bit per chip system has 16 lots of 1 Mbit chip with bit 1 of each word in chip 1 and so on A 16 Mbit chip can be organised as a 2048 x 4 bit array n Reduces number of address pins – Multiplex row address and column address – 11 pins to address (211=2048) – Adding one more pin doubles range of values so x 4 capacity (212 x 4 Capacity with 211) 15

Refreshing l l l Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance 16

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Typical 16 Mb DRAM (4 M x 4) 18

Packaging 19

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Module Organisation l l 256 Kbit per Chip 8 chips to construct 256 KB 21

Module Organisation (2) 22

Error Correction l Hard Failure n l Soft Error n n l Permanent defect Random, non-destructive No permanent damage to memory Detected using Hamming error correcting code 23

Error Correcting Code Function 24

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Advanced DRAM Organization l l Basic DRAM same since first RAM chips Enhanced DRAM n n l Contains small SRAM as well SRAM holds last line read (c. f. Cache!) Cache DRAM n n Larger SRAM component Use as cache or serial buffer 27

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Synchronous DRAM (SDRAM) l l l l Access is synchronized with an external clock Address is presented to RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) 30

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IBM 64 Mb SDRAM 32

SDRAM Operation 33

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