Welcome to Technical Seminar Tour 2007 LATTICES PROGRAMMABLE

Welcome to Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS Technical Seminar Tour 2006 - Page 1 Mach. XO / XP / Overview

Non-volatile Solutions Lattice Mach 4000 Lattice Mach. XO Lattice Mach. XP TM TM TM Jörg Siemers, TMM; Avnet-Memec Technical Seminar Tour 2006 - Page 2 Mach. XO / XP / Overview

Mach 4000 1000 isp. MACH CPLD Mach. XO Crossover Lattice. XP FPGA I/O 100 1000 Registers Technical Seminar Tour 2006 - Page 3 Mach. XO / XP / Overview 100000

isp. MACH 4000 Family Overview ¨ Super. FAST CPLD Family 400 MHz f. MAX and 2. 5 ns t. PD for highsystem performance ¨ Low Static Power Full CMOS design with static power as low as 40 W (Z-type) ¨ Low Dynamic Power 1. 8 V core for low dynamic power consumption ¨ Flexible Architecture Get designs to market fast ¨ Flexible Solution - 32 to 512 macrocells - 3. 3 V, 2. 5 V or 1. 8 V supply - Commercial/Industrial/Automotive Technical Seminar Tour 2006 - Page 4 Mach. XO / XP / Overview

isp. MACH 4000 - Optimal CPLD Solutions 300 Lattice 200 ORP Generic Logic Block Global Routing Pool (GRP) Generic Logic Block ORP I/O Block BANK 1 I/O Block Lattice Leadership BANK 0 f. MAX (MHz) 400 Competition A Competition B I/O Block 100 256 512 768 ORP Generic Logic Block I/O Block 1024 Density (Macrocells) Super. FAST Performance Flexible Architecture Mainstream CPLDs Zero Power • 1. 8/2. 5/3. 3 V Power Supply • 1. 8/2. 5/3. 3/5 V I/O • 32 to 512 Macrocells • Commercial/Industrial/ Automotive Technical Seminar Tour 2006 - Page 5 Mach. XO / XP / Overview

isp. MACH 4000 Family rts Suppo. 3 V , or 3 1. 8, 2. 5 upply S Power Technical Seminar Tour 2006 - Page 6 Mach. XO / XP / Overview

isp. MACH 4000 Automotive Applications 4000 Automotive Features ü Operation – 40 OC to 125 OC ü Highest Performance ü Design Flexibility ü Lowest Power Consumption ü 1. 8, 2. 5 and 3. 3 V I/O (with 5 V Tolerance) Technical Seminar Tour 2006 - Page 7 Mach. XO / XP / Overview

isp. MACH 4000 V Automotive Family V 4032 V 4064 V 4128 4256 V Macrocells 32 64 128 256 f. MAX(MHz) t. PD (ns) t. CO (ns) t. S (ns) 168 7. 5 4. 5 30/32 30/ 32/64 64/92/96 64/96/128 44 TQFP 48 TQFP 100 TQFP 128 TQFP 144 TQFP 100 TQFP I/O Packages Technical Seminar Tour 2006 - Page 8 Mach. XO / XP / Overview 144 TQFP 176 TQFP

isp. MACH 4000 Z Automotive Family Z 4032 Z 4064 Z 4128 4256 Macrocells 32 64 128 256 f. MAX(MHz) t. PD (ns) t. CO (ns) t. S (ns) 150 7. 5 4. 5 I/O 32 32/64 64/92 64/128 48 TQFP 100 TQFP 176 TQFP Packages Technical Seminar Tour 2006 - Page 9 Mach. XO / XP / Overview Z

Mach. XO Crossover 10000 1000 isp. MACH CPLD Mach. XO Crossover Lattice. XP FPGA I/O 100 1000 Registers Technical Seminar Tour 2006 - Page 10 Mach. XO / XP / Overview 100000

FLASH Bringing the Best Together Reconfigurable MACHXO Non-Volatile FPGAs without Compromise Technical Seminar Tour 2006 - Page 11 Mach. XO / XP / Overview SRAM

Geometry Fujitsu Technology Partnership 130 nm Logic 130 nm Flash + Logic 1. 2 -volt core q Proven 130 nm and 90 nm q Industry Leading 130 nm Flash q 300 mm Fab for Lower Costs q 65 nm Development Underway 90 nm Logic Fujitsu & Lattice Bringing the Best Together Time Technical Seminar Tour 2006 - Page 12 Mach. XO / XP / Overview 65 nm Logic

Mach. XO Brings the Best Together Attribute CPLD High Pin-to-Pin Speed Fast Wide Logic High I/O to Logic Ratio Instant-On Register Intensive Distributed & Embedded Memory FPGA Mach. XO Mach. XO Brings Together CPLD and FPGA Attributes to Optimally Serve Traditional CPLD Applications Technical Seminar Tour 2006 - Page 13 Mach. XO / XP / Overview

Mach. XO Key Features ¨ Non-Volatile Solution – Single chip, instant-on, high security ¨ Trans. FR™ (TFR) Technology – Simplifies in-field logic updates ¨ High Performance – 3. 5 n pin-to-pin* ¨ LUT Based Flexibility – 256 to 2, 280 (LUT 4 s) – 2 K to 8 K bits distributed memory ¨ I/O Intensive – 78 to 271 I/O ¨ Flexible sys. IOTM Buffers – LVCMOS 33/25/18/15/12, LVDS**, PCI** ¨ sys. MEMTM Block Memory ** – Up to 28 K bits of memory LUT Flexibility Non-volatility Embedded Memory Performance ¨ sys. CLOCKTM PLLs** ¨ On Board Oscillator ~20 MHz ¨ 1. 2/1. 8/2. 5/3. 3 V Power Supply Options – Low standby power (2 m. A @ 640 LUTs) Technical Seminar Tour 2006 - Page 14 Mach. XO / XP / Overview

Mach. XO Block Diagram (1200 and 2280) sys. CLOCK PLLs Frequency Synthesis & Clock Alignment sys. IO Buffers Support LVCMOS/LVTTL, LVDS and PCI Programmable Function Units (PFUs) (with RAM) sys. MEM Block RAM 9 kbit Dual Port Programmable Function Units (PFFs) (without RAM) Flexible Routing Optimized for Speed, Cost and Routability Technical Seminar Tour 2006 - Page 15 Mach. XO / XP / Overview JTAG Port

Mach. XO Block Diagram (640 and 256) Mach. XO 640 Programmable Function Units (PFUs) (with RAM) Four banks of sys. IO Buffers Support LVCMOS/LVTTL Programmable Function Units (PFFs) (without RAM) Flexible Routing Optimized for Speed, Cost and Routability JTAG Port Mach. XO 256 Two banks of sys. IO Buffers Support LVCMOS/LVTTL Technical Seminar Tour 2006 - Page 16 Mach. XO / XP / Overview

Mach. XO Configuration Options On Chip FLASH Single Chip Solution Excellent Security FLASH MEMORY Control Logic SRAM Config. Bits (Control Device Op. ) Massively Parallel Wide Data Transfer Provides. Fast SRAM Configuration from FLASH “Instant-on” Mach. XO Infinitely Reconfigure SRAM Through JTAG Port Reprogram FLASH Through JTAG Port • Flash Configures Logic, Interconnect and Block RAM for User PROMs • Trans. FR (TFR) Technology Simplifies In-Field Logic Updates Technical Seminar Tour 2006 - Page 17 Mach. XO / XP / Overview

Mach. XO Simplifies In-Field Logic Updates Requirement Mach. XO with Trans. FR (TFR) Technology Embedded Programming Minimum Downtime I/O States Preserved Device State Controlled isp. VM Embedded Background Program Update SRAM <1 m. S XFLASH Trans. FR isp. VM Command Controls I/O & Device State Transparent Field Reconfiguration (Trans. FR) Technical Seminar Tour 2006 - Page 18 Mach. XO / XP / Overview

sys. IO Interfaces ¨ sys. IO Buffer Supports Multiple I/O Standards ¨ Hotsocketing – LVTTL, LVCMOS 33/25/18/15/12 – PCI* – LVDS*, BLVDS**, LVPECL** ¨ Up to 8 I/O Banks For Flexibility in I/O Placement Output data OE Output data GOE TO DO Fast output data signal PAD – Input leakage less than 1 m. A during power-up/power-down – Power supplies can be sequenced in any order ¨ Programmable Slew Rate ¨ Programmable Drive Strength – – – 4 to 20 m. A (3. 3 -volts) 4 to 20 m. A (2. 5 -volts) 4 to 16 m. A (1. 8 -volts) 4 to 8 m. A (1. 5 -volts) 2 to 6 m. A (1. 2 -volts) ¨ Programmable Pull-up, Pulldown, Bus-friendly ¨ Programmable Open Drain Input data signal Programmable delay element * Mach. XO 1200 and 2280 ** Mach. XO 1200 and 2280 with external resistors Technical Seminar Tour 2006 - Page 19 Mach. XO / XP / Overview

sys. MEM Block RAM ¨ Provides 9, 216 Bit Blocks Single Port Dual Port ¨ 275 MHz Operation 8, 192 X 1 4, 096 X 2 2, 048 X 4 1024 X 9 512 X 18 256 X 36 ¨ Efficient Implementation of Buffers AD[12: 0] DI[35: 0] CLK RST WE CS[2: 0] RAM (Single Port) (Dual Port) EBR ADA[12: 0] DIA[17: 0] CLKA DO[35: 0] RSTA WEA CSA[2: 0] DOA[17: 0] EBR ADB[12: 0] DIB[17: 0] CLKB RSTB WEB CSB[2: 0] DOB[17: 0] RAM ROM 8, 192 X 1 4, 096 X 2 2, 048 X 4 1024 X 9 512 X 18 EBR WD[35: 0] WCLK WCE WE RST EBR 8, 192 X 1 4, 096 X 2 2, 048 X 4 1024 X 9 512 X 18 256 X 36 ¨ Single Port, Dual Port , Pseudodual Port, FIFO and ROM Modes ¨ FIFO Logic Included in EBR FIFO (Pseudo Dual Port) DO[35: 0] 8, 192 X 1 4, 096 X 2 2, 048 X 4 1024 X 9 512 X 18 256 X 36 FIFO ¨ Configurable Width and Depth WAD[12: 0] CLK CE Pseudo Dual Port RAD[12: 0] RD[35: 0] RCE RCLK Technical Seminar Tour 2006 - Page 20 Mach. XO / XP / Overview

sys. CLOCK PLL Dynamic Delay Adjust CLOCK IN (From pin or routing) Divider (1 -12) LOCK Delay Adjust PLL Divider (2, 4, , 24) Phase & Duty Select CLOCK OUT 0. 25 ns Steps +/- 2 ns Range Feedback (From post scalar divider, clock net or external pin) Divider (2, 4, , 128) Divider (1 -12) CLOCK OUT • Frequency: 25 MHz - 420 MHz – VCO Frequency 420 -840 MHz • Low Output Period Jitter: ~ +-120 ps • Programmable Phase /Duty Cycle (45 Degree Steps) • Dynamic Delay Adjust – Increments of 250 ps with a total of 2 ns lead or 2 ns lag Technical Seminar Tour 2006 - Page 21 Mach. XO / XP / Overview

Multiple Power Supply Options 1. 2 Volts VCCP 3. 3 Volts VCCAUX 1. 2 to 3. 3 V for Chosen I/O Std. VCCJ VCCIO Mach. XO VCCP VCC 3. 3 Volts VCCAUX 1. 2 to 3. 3 V for Chosen I/O Std. VCCJ Mach. XO Internal logic operates at 1. 2 -volts Lower Voltage (E) Version 3. 3/2. 5/1. 8 Volts Internal logic operates at 1. 2 -volts Upper Voltage (C) Version ¨ Use C Version to Access Latest Technology Without Adding New Power Supplies to Board – Improve performance and power consumption – Allows single supply operation from 3. 3 -volts ¨ Use E Version to Minimize Power Consumption – 64% lower power than operation at 3. 3 -volts Technical Seminar Tour 2006 - Page 22 Mach. XO / XP / Overview VCCIO

Sleep Mode Reduces Power by Factor of 1000 SLEEPN Pin Device State Lattice. XO Normal Sleep Mode Typical 100 n. S Normal Typical 1 m. S Mode Characteristic Normal Off Sleep High X Low Typical <100 m. A 0 Typical <100 u. A Power Supplies Normal Range Off Normal Range Logic Operation User Defined Non Operational I/O Operation User Defined Tri-State SLEEPN Pin Static Icc Note: Sleep Mode is only available on 1. 8/2. 5/3. 3 V “C” version Technical Seminar Tour 2006 - Page 23 Mach. XO / XP / Overview

Mach. XO Benefits Self-Configuration in Under A Millisecond • Instant-On ideal for system “heartbeat” control logic • Supports configuration “scrubbing” for SEU control • Supports rapid power cycling Single Chip High Security • Simplify design • Reduced PCB footprint • Save boot PROM costs • Security bits prevent readback • No exposed power-up bitstream SRAM + FLASH • Trans. FR (TFR) technology enables in field updates while system operates Technical Seminar Tour 2006 - Page 24 Mach. XO / XP / Overview On-Chip Regulation • Support legacy applications with latest technology - Reduce costs - Improve performance

Mach. XO Family Members Device LCMXO 256 LCMXO 640 LUTs Distributed RAM (KBits) EBR SRAM (KBits) # EBR SRAM Blocks (9 Kb) VCC Voltage 256 2 0 0 640 6. 1 0 0 Number of PLLs Max I/O Packages: 100 -TQ (14 X 14) 144 -TQ (20 X 20) cs. BGA 100 (8 X 8) cs. BGA 132 (8 X 8) fp. BGA 256 (17 X 17) fp. BGA 324 (19 X 19) 0 78 78 78 LCMXO 1200 LCMXO 2280 1200 6. 4 9. 2 1 1. 2/1. 8/2. 5/3. 3 V 0 1 159 211 2280 7. 7 27. 6 3 74 113 74 101 159 73 113 101 211 271 Technical Seminar Tour 2006 - Page 25 Mach. XO / XP / Overview 2 271

LA-Mach. XO Family XO LAM 256 XO LAM 640 XO LAM 1200 XO LAM 2280 LUTs 256 640 1200 2280 sys. MEM Blocks (9 Kbits) sys. MEM EBR RAM (bits) Distributed RAM (k bits) 0 0 2. 0 0 0 6. 1 1 9216 6. 4 3 27648 7. 7 0 4 LVCMOS 2 4 LVCMOS PCI LVDS 78 74 113 159 73 113 211 271 No Plan 1 sys. CLOCK PLLs Global Clocks I/O Type Pb-Free Packages / IO 100 TQFP 144 TQFP 256 ft. BGA 324 ft. BGA Availability (E = 1. 2 V) (C = 3. 3/2. 5/1. 8 V) 1. Due to thermal consideration. Technical Seminar Tour 2006 - Page 26 Mach. XO / XP / Overview

Mach. XO Summary ¨ Mach. XO Offers a Unique Combination of Flash and SRAM Technology to Deliver Non-Volatile, In. System Reconfigurable Logic ¨ Mach. XO Offers an Extremely Cost-Effective Alternative to High-End CPLDs and Low-End FPGAs with the Best Features of Both ¨ Applications for Mach. XO Span All Market Segments and Electronic Systems ¨ The Combination of Lattice. EC/ECP/XP FPGAs and Mach. XO Gives Lattice the Broadest Portfolio of Low-Cost FPGAs Available Technical Seminar Tour 2006 - Page 27 Mach. XO / XP / Overview

XP - non volatile FPGA Family 10000 1000 isp. MACH CPLD Mach. XO Crossover Lattice. XP FPGA I/O 100 1000 Registers Technical Seminar Tour 2006 - Page 28 Mach. XO / XP / Overview 100000

FLASH Bringing the Best Together Reconfigurable isp. XP Non-Volatile FPGAs without Compromise Technical Seminar Tour 2006 - Page 29 Mach. XO / XP / Overview SRAM

Fujitsu Technology Partnership Geometry 130 nm Logic 1. 2 -volt core q Proven 130 nm and 90 nm q Industry Leading 130 nm Flash q 300 mm Fab for Lower Costs q 65 nm Development Underway 130 nm Flash + Logic 1. 2 -volt core 90 nm Logic Fujitsu & Lattice Bringing the Best Together Time Technical Seminar Tour 2006 - Page 30 Mach. XO / XP / Overview 65 nm Logic

Lattice. XP FPGA Key Features ¨ Non-Volatile Reconfigurable ¨ Low Cost Solution – Optimized architecture – 0. 13 um Flash process ¨ Wide Density & I/O Selection – 3 k to 20 k LUTs – 62 to 340 I/Os ¨ Embedded & Distributed Memory – 12 kbits to 79 kbits distributed in LUTs – 54 kbits to 414 kbits embedded block ¨ High Performance (225 MHz+) ¨ sys. IO™ Interface Support – LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL Non-Volatile Reconfigurable Flexible LUT-Based “No Compromise” ¨ 333 Mbps DDR Memory Interfaces ¨ sys. CLOCK™ PLLs ¨ Two Core Power Supply Versions – C = 1. 8, 2. 5, 3. 3 V Support – E = 1. 2 V Support Technical Seminar Tour 2006 - Page 31 Mach. XO / XP / Overview

Lattice. XP: Added Non-Volatility isp. XP FLASH Memory Instant-on, Secure and Single-chip sys. CLOCKTM PLLs Frequency Synthesis & Clock Alignment sys. MEMTM Block RAM 9 kbit Dual Port JTAG Optimized sys. IOTM Buffers Support Mainstream I/O: LVCMOS/LVTTL, LVDS, SSTL, HSTL, DDR Memory Interfaces Optimized Programmable Function Units (PFUs) 25% – Logic + RAM 75% – Logic Only Flexible Routing Optimized for Speed, Cost and Routability Technical Seminar Tour 2006 - Page 32 Mach. XO / XP / Overview

Lattice. XP Configuration Options On Chip Non-Volatile Single Chip Solution Excellent Security FLASH MEMORY SRAM Configuration Bits (Control Device Operation) Control Logic Massively Parallel Data Transfer & Multiple Blocks Provide Secure and Fast SRAM Configuration “Instant-on” sys. CONFIG Port JTAG Port Control Logic FLASH MEMORY Parallel sys. CONFIG™ to Configure SRAM or Program FLASH Serial JTAG Port (IEEE 1532/1149. 1) to Configure SRAM or Program FLASH Flash Configures Logic, Interconnect and Block RAM for User PROMs Background Flash Programming Support - Upgrade system remotely Leave-Alone I/O - Control I/O state while refreshing Technical Seminar Tour 2006 - Page 33 Mach. XO / XP / Overview

Logic operates based on SRAM configuration #1 FLASH Programming During Device Operation FLASH (#2) Program configuration #2 to FLASH via sys. CONFIG or JTAG ports FLASH (#1 #2) Background Programming With Lattice. XP Logic operates based on SRAM configuration #2 ¨ Background Programming of Flash Occurs While the Device is in Normal Operation ¨ Power Cycle or Apply a Refresh Command ¨ New/Updated Configuration Takes Control Reload SRAM at Power-up or User Command Technical Seminar Tour 2006 - Page 34 Mach. XO / XP / Overview

XP 10 Programming Times Reconfigurable isp. XP ¨ SRAM Configuration Non-Volatile – From FLASH 2 ms – Via sys. CONFIG 11 ms – Via JTAG 100 m. S ¨ FLASH Programming* – Via JTAG 2 Seconds – Via sys. CONFIG 2 Seconds * Programming time. Erase approximately 10 seconds Technical Seminar Tour 2006 - Page 35 Mach. XO / XP / Overview

Lattice. XP Wake-up Time 140 XP Advantage Altera Wake-up Time (m. S) 120 100 80 60 Xilinx 40 20 Lattice 0 EP 1 C 12 XC 3 S 1000 XP 10 Fastest serial configuration Lattice. XP Logic is Available 1 m. S After Power Good -- Supports “Instant-on” Application Requirements -Technical Seminar Tour 2006 - Page 36 Mach. XO / XP / Overview

Lattice. XP Integrates Multiple Components FPGA Data Path function Voltage Regulator Technical Seminar Tour 2006 - Page 37 Mach. XO / XP / Overview Microprocessor Processor Address and Data Busses CPLD Power up logic FPGA boot logic and bus decode Processor Address and Data Busses Microprocessor

Lattice. XP FPGAs Secure Your Design ¨ FPGA Security Important Due To Multiple Threats – – 01101101001 Lattice. XP FPGAs Secure Your Design Reverse engineering Cloning Overbuilding Theft of service ¨ Lattice. XP Security Scheme Allows Devices To Be Locked – Secures SRAM and FLASH – Erasing memory is only allowable operation – 0. 13 um technology and 8 metal layers makes probing next to impossible 0100101 ¨ Specify Secure Mode in isp. LEVER or isp. VM 011011010010101 SRAM FPGAs Expose Your Intellectual Property At Power Up Technical Seminar Tour 2006 - Page 38 Mach. XO / XP / Overview

Optimized PFU Logic Block Carry Chain Cyclone 0% Distributed Memory Impacts Logic Efficiency SLICE 3 LUT 4 FF LUT 4 Spartan 3 50% Distributed Memory Incurs Unnecessary Die Cost SLICE 2 FF LUT 4 FF To Routing SLICE 1 LUT 4 FF Frequency of Usage (>250 Designs) FF LUT 4 From Routing Optimized Lattice. XP Devices Support 25% Distributed Memory 10% LUTs Needed for Distributed Memory on Average 0% LUT 4 LUTs Used As Distributed Memory 50% FF SLICE 0 LUT 4 FF FF Logic Block (PFU) Carry Chain ¨ Industry-standard 4 -input LUT Structure – Combine multiple LUTs for larger functions – Carry Chain for arithmetic speed Optimized Architecture Delivers Uncommon Value Technical Seminar Tour 2006 - Page 39 Mach. XO / XP / Overview

sys. MEM Block RAM ¨ Provides 9, 216 Bit Blocks ¨ 250 MHz Operation ¨ Multiple Blocks per Device AD[12: 0] DI[35: 0] CLK RST WE CS[2: 0] RAM (Single Port) (Dual Port) EBR ADA[12: 0] DIA[17: 0] CLKA DO[35: 0] RSTA WEA CSA[2: 0] DOA[17: 0] EBR ADB[12: 0] DIB[17: 0] CLKB RSTB WEB CSB[2: 0] DOB[17: 0] RAM ROM (Pseudo Dual Port) WAD[12: 0] CLK CE EBR DO[35: 0] WD[35: 0] WCLK WCE WE RST EBR Single Port Dual Port 8, 192 X 1 4, 096 X 2 2, 048 X 4 1, 024 X 9 512 X 18 256 X 36 RAM RAD[12: 0] RD[35: 0] RCE RCLK Pseudo. Dual Port 256 X 36 ¨ Configurable Width and Depth ¨ Single Port, Dual Port , Pseudodual Port and ROM Modes ¨ Port Width Matching ¨ FIFO with surrounding logic Technical Seminar Tour 2006 - Page 40 Mach. XO / XP / Overview

sys. CLOCK PLL Dynamic Delay Adjust CLOCK IN (From pin or routing) LOCK Input Clock Divider (CLKI) Delay Adjust PLL Post Scalar Divider (CLKOP) Phase & Duty Select CLOCK OUT 0. 25 ns Steps +/- 2 ns Range Secondary Clock Divider (CLKOK) Feedback Divider (CLKFB) Feedback (From post scalar divider, clock net or external pin) CLOCK OUT ¨ Frequency Range 25 to 375 MHz ¨ ¨ ¨ - VCO range 420 to 750 MHz Analog PLL Technology Low Output Period Jitter (+/- 125 ps) Programmable Phase / Duty Cycle (45 degree steps) Programmable Dividers Internal and External Feedback Technical Seminar Tour 2006 - Page 41 Mach. XO / XP / Overview

PIC 2 -FF Output & Tristate Structure Allows Easy DDR Implementation PIO A PIC Tri-state Register Block (2 Flip/flops) 5 -Flip Flop Input Structure Allows Easy DDR Implementation (Including clock domain transfer) Output Register Block (2 Flip/flops) Input Register Block (5 Flip/flops) High performance sys. IO Buffer (700 Mbps) Input Dedicated Circuitry Simplifies DDR Memory Implementations (up to 333 Mbps) * Selected blocks Control Select DQS Delay and Transition Detect* PIO B (Detail Not Shown) Technical Seminar Tour 2006 - Page 42 Mach. XO / XP / Overview 8 I/O Banks Allows Flexible I/O Implementation

I/O Banking Scheme GND VREF 2(1) VREF 1(1) VCCIO 1 GND VREF 2(0) VREF 1(0) VCCIO 0 ¨ Eight I/O Banks Per Device Bank 0 VREF 2(7) VCCIO 2 Bank 2 VREF 1(7) Bank 7 VCCIO 7 Bank 1 GND VCCIO 6 Bank 6 GND ¨ LVCMOS Inputs – 12, 25 & 33 independent of VCCIO – 15 & 18 dependent on VCCIO VREF 2(3) GND ¨ Multiple Compatible I/O Standards In A Bank GND VREF 2(4) ¨ Referenced Inputs Dependent on VREF 1(3) Bank 4 VCCIO 4 GND VREF 2(5) VCCIO 5 Bank 5 VREF 1(4) GND VREF 1(5) V REF 2(6) VREF 2(2) VCCIO 3 Bank 3 VREF 1(6) VREF 1(2) ¨ Output Standard Support Dependent on VCCIO Technical Seminar Tour 2006 - Page 43 Mach. XO / XP / Overview

DDR Memory Interfaces DDR to SDR De-mux Half Clock Transfer ¨ DDR DRAM is the Low-Cost Memory of Choice Input Logic Block Data Automatic Clock Transfer Circuitry Simplifies Design & Ensures Robust Operation DLL Calibrated DQS to DQ Alignment Lattice. XP Pre-Engineered DDR Interfaces Clock Polarity Select* DQS Delay Block* * Selected Input Logic Blocks ¨ DDR Memory Interface Issues – – Precision DQS Delay Control Dedicated DDR Registers (Fast Muxing/Demuxing) Automatic DQS to System Clock Domain Transfer Half Clock Transfer High-Performance 166 MHz 333 Mbps (Temp. & Voltage-Compensated) DQS DDRCLKPOL – >50% of 2004 Total DRAM Bits Bi-directional DQ & DQS Tight timing specifications Clock domain transfers Muxing/de-muxing data DQS Exceptional DDR Performance Technical Seminar Tour 2006 - Page 44 Mach. XO / XP / Overview

Multiple Power Supply Options 1. 2 Volts VCCP 3. 3 Volts VCCAUX 1. 2 to 3. 3 V for Chosen I/O Std. VCCJ VCCIO Internal logic operates at 1. 2 -volts Lower Voltage (E) Version 3. 3/2. 5/1. 8 Volts VCCP VCC 3. 3 Volts VCCAUX 1. 2 to 3. 3 V for Chosen I/O Std. VCCJ Internal logic operates at 1. 2 -volts Upper Voltage (C) Version ¨ Use C Version to Access Latest Technology Without Adding New Power Supplies to Board – Improve performance and power consumption – Allows single supply operation from 3. 3 -volts ¨ Use E Version to Minimize Power Consumption – 64% lower power than operation at 3. 3 -volts Technical Seminar Tour 2006 - Page 45 Mach. XO / XP / Overview VCCIO

Sleep Mode Reduces Power by Factor of 1000 SLEEPN Pin Device State Lattice XP Normal Sleep Mode Typical 100 n. S Normal Typical 2 m. S Mode Characteristic Normal Off Sleep High X Low Typical <100 m. A 0 Typical <100 u. A Power Supplies Normal Range Off Normal Range Logic Operation User Defined Non Operational I/O Operation User Defined Tri-State SLEEPN Pin Static Icc Note: Sleep Mode is only available on 1. 8/2. 5/3. 3 V “C” version Technical Seminar Tour 2006 - Page 46 Mach. XO / XP / Overview

Lattice. XP Benefits Self-Configuration in Under A Millisecond • Ideal for system “heartbeat” control logic • Supports configuration “scrubbing” for SEU control • Supports rapid power cycling Single Chip High Security • Simplify design • Reduced PCB footprint • Save boot PROM costs • Security bits prevent readback • No exposed power-up bitstream SRAM + FLASH • Real time programming of device during operation Technical Seminar Tour 2006 - Page 48 Mach. XO / XP / Overview On-Chip Regulation • Support legacy applications with latest technology - Reduce costs - Improve performance

Lattice. XP Family Device XP 3 XP 6 XP 10 XP 15 XP 20 3. 1 5. 8 9. 7 15. 4 19. 7 sys. MEM Blocks 6 10 24 32 46 sys. MEM (Kbits) 54 90 216 288 414 Distributed RAM (Kbits) 12 23 39 61 79 4 4 4 188 188 244 268 300 340 LUTs (K) Voltage (V) PLLs 1. 2/1. 8/2. 5/3. 3 V 2 2 Package I/O Combinations 100 -pin TQFP (14 x 14 mm) 62 144 -pin TQFP (20 x 20 mm) 100 208 -pin PQFP (28 x 28 mm) 136 142 256 -ball fp. BGA (17 x 17 mm) 388 -ball fp. BGA (23 x 23 mm) 188 484 -ball fp. BGA (23 x 23 mm) Technical Seminar Tour 2006 - Page 49 Mach. XO / XP / Overview

Lattice. XP Value Proposition ¨ Non-Volatile FPGA – Single Chip – High Security – Instant-On ¨ Mainstream LUT-based Architecture ¨ Optimized Device Provides Low Cost Solution – Manufacturable 130 nm silicon process ¨ Best DDR Memory Support – Easy design of 333 Mbps interfaces ¨ Popular Packaging Options – TQFP, PQFP, fp. BGA – Ro. HS / Lead-Free available Combines the Best of Non-Volatile & SRAM -- No Compromise FPGA! Technical Seminar Tour 2006 - Page 50 Mach. XO / XP / Overview

Lattice Product Families 10000 1000 Lattice. SC Lattice. ECP/2/XP/ System Chip Mach. XO FPGA isp. MACH Crossover CPLD I/O 100 10000 Density Technical Seminar Tour 2006 - Page 51 Mach. XO / XP / Overview 100000

Technical Seminar Tour 2006 - Page 52 Mach. XO / XP / Overview

Lattice. SC Architecture High Performance FPGA Fabric 4 to 32 SERDES (Up to 3. 4 Gbps) with Physical Coding Sublayer (PCS) 2 Gbps PURESPEED I/O 15 K to 115 K LUT 4 s Up to 7. 8 Mbits of Embedded Memory Blocks MACO: Embedded Structured ASIC Blocks (Lattice. SCM Devices) 1. 0 V-1. 2 V Operating Voltage 8 Analog PLLs / 12 DLLs per Device Technical Seminar Tour 2006 - Page 53 Mach. XO / XP / Overview System-Level Features: Embedded System Bus / Dedicated Microprocessor Interface / SPI Flash Configuration

Masked Array for Cost Optimization ¨ Multiple 90 nm Embedded 50 K ASIC Blocks ¨ Ample FPGA-to-ASIC Signal Connectivity ¨ Ample ASIC-to-IO Connectivity ¨ High-speed Clock Connectivity Technical Seminar Tour 2006 - Page 54 Mach. XO / XP / Overview

SERDES Quad EMB SERDES Quad MACO: Standard Offerings MACO A A EMB B A C C EMB F C E B EMB DB PLC Array Lattice. SCM 25 Technical Seminar Tour 2006 - Page 55 Mach. XO / XP / Overview

Lattice. SC(M) Family Device SC 15 SC 25 SC 40 SC 80 SC 115 15. 2 25. 4 40. 4 80. 1 115. 2 56 104 216 308 424 Embedded Memory (Mbits) 1. 03 1. 92 3. 98 5. 68 7. 8 Distributed Memory (Mbits) 0. 24 0. 41 0. 65 1. 28 1. 84 8 16 16 32 32 8 / 12 8 / 12 4 6 10 10 12 1152 -ball fc. BGA (35 x 35) 660+16 1704 -ball fc. BGA (42. 5 x 42. 5) 904+32 942+32 LUTs (K) sys. MEM Blocks (18 Kb) 3. 4 Gbps SERDES PLLs / DLLs MACO Blocks* Package I/O + SERDES Combinations (1 mm Ball Pitch) 256 -ball fp. BGA (17 x 17) 139+4 900 -ball fp. BGA (31 x 31) 300+8 1020 -ball ff. BGA (33 x 33) 378+8 484+16 562+16 *Maximum Number of 50 K Gate MACO Blocks. MACO Enabled Only on Lattice. SCM Family Technical Seminar Tour 2006 - Page 56 Mach. XO / XP / Overview

isp. LEVER® Design Tools OEM Tools integrated: • Mentor Graphics Precision • Synplicity Synplify • Model Technologie Model. Sim Technical Seminar Tour 2006 - Page 57 Mach. XO / XP / Overview

isp. LEVER Configuration Options isp. LEVER - Device Support Synthesis Support Simulation License Type All Lattice Programmable Logic: All Devices n/a Floating (UNIX/LINUX) Node Locked or Floating (PC) Mentor Model. Sim 6. 1 a 2005 b Lattice Functional Simulator Node Locked or Floating Stand-Alone Compiler Includes Lattice device libraries to work with 3 rd party EDA environments. (PC, UNIX) isp. LEVER Base HDL isp. LEVER Starter All Devices Für Seminar. Teilnehmer: 295€ New / Focus CPLD, Mach. XO, XPGA, GDX EC, ECP, XP 3 -XP 6 Intended for evaluation, and student users, isp. LEVER Starter is a complete solution that can take your design from concept through device programming. (PC) Precision Synplicity Synplify 8. 2 h Mentor Precision 2005 b Synplicity Lattice Functional Simulator Synplify 8. 2 h Free SW Technical Seminar Tour 2006 - Page 59 Mach. XO / XP / Overview Node Locked: 6 -Month Trial

isp. TRACY Debugging Environment Technical Seminar Tour 2006 - Page 60 Mach. XO / XP / Overview

Lattice IP Support ¨ PCI ¨ DDR I ¨ 1 GB Ethernet MAC ¨ 10/100 Ethernet MAC ¨ QDR II ¨ SDRAM ¨ DMA ¨ I 2 C ¨ …. . and more see www. latticesemi. com Evaluation Board Allows Many IPs to Be Checked Out In The Lab Technical Seminar Tour 2006 - Page 61 Mach. XO / XP / Overview

Jump. In 2 Practice by e. Vision Systems Get your ideas into the market, FAST - FPGA relevant Training content - All tutorials based on isp. LEVER - Support you with BASIC and ADVANCED Course - Training Material that will become your day to day working book for the future YOUR SUCCESS IS OUR MISSION Technical Seminar Tour 2006 - Page 62 Mach. XO / XP / Overview

Jump. In 2 Practice About e. Vision Systems - independent EDA Company based in the Munich area - VHDL, Verilog and System. C Tools - RFIC & MICROWAVE Design Tools - Technical Support Team - Training Services - Own HDL Design Experience www. evision-systems. de www. jumpin 2 practice. de Technical Seminar Tour 2006 - Page 63 Mach. XO / XP / Overview