Week 5 Virtual Memory CS 162 Todays Section

Week 5: Virtual Memory CS 162

Today’s Section • • Administrivia Quiz Review of Lecture Worksheet and Discussion

Administrivia • Project 2 – Initial Design Documents due Next Thursday, March 6 th! – Get started early, not as straightforward – Signups should be up by this weekend! – Fill out midterm course surveys! – Check out Project 2 Overview for Nachos on Piazza! • Midterm 1 is 3/12, 4: 00 -5: 30 pm in 245 Li Ka Shing (A-L) and 105 Stanley (M-Z) – Covers lectures 1 -12, readings, handouts, projs 1 & 2

Address Translation and Caching LECTURE REVIEW

Address Translation • Translation – Changing the virtual address to a physical one • Allows the program to think that we have more space than we actually do • Provides a way to overlap to share memory between processes if need be

Example of General Address Translation Data 2 Code Data Heap Stack 1 Heap 1 Code 1 Stack 2 Prog 1 Virtual Address Space 1 Prog 2 Virtual Address Space 2 Data 1 Heap 2 Code 2 OS code Translation Map 1 OS data Translation Map 2 OS heap & Stacks Physical Address Space

Issues with Simple Segmentation Method process 6 process 5 process 9 process 2 OS process 6 process 9 process 11 process 10 OS OS OS • Fragmentation problem – Not every process is the same size – Over time, memory space becomes fragmented • Hard to do inter-process sharing – Want to share code segments when possible – Want to share memory between processes – Helped by providing multiple segments per process

Schematic View of Swapping • Q: What if not all processes fit in memory? • A: Swapping: Extreme form of Context Switch – In order to make room for next process, some or all of the previous process is moved to disk – This greatly increases the cost of context-switching • Desirable alternative? – Some way to keep only active portions of a process in memory at any one time – Need finer granularity control over physical memory

Page Table Types • Page Table – Maps a virtual page to a physical page • Multi-Level Page Tables – Each part of the address is split apart for each level of the table to get more spread. More memory accesses • Inverted Page Table – Hash Table used to map virtual addresses to physical ones • Remember a page table has to fit within one page!

Address Translation Comparison Advantages Disadvantages Segmentation Fast context External fragmentation switching: Segment mapping maintained by CPU Paging (single No external -level page) fragmentation, fast easy allocation Large table size ~ virtual memory Paged Table size ~ # of segmentation pages in virtual memory, fast easy Two-level allocation pages Multiple memory references per page access Inverted Table size ~ # of pages in physical 2/24/2014 Anthony D. memory Joseph CS 162 Hash function more complex ©UCB Spring 2014 9. 10

Caching Concept • Cache: a repository for copies that can be accessed more quickly than the original – Make frequent case fast and infrequent case less dominant • Caching at different levels – Can cache: memory locations, address translations, pages, file blocks, file names, network routes, etc… • Only good if: – Frequent case frequent enough and – Infrequent case not too expensive • Important measure: Average Access time = (Hit Rate x Hit Time) + (Miss Rate x Miss Time) 2/26/14 Anthony D. Joseph CS 162 ©UCB Spring 2014 Lec 10. 11

Why Does Caching Help? Locality! Probability of reference 0 2 n - 1 Address Space • Temporal Locality (Locality in Time): – Keep recently accessed data items closer to processor • Spatial Locality (Locality in Space): – Move contiguous blocks to the upper levels To Processor Upper Level Memory Lower Level Memory Blk X From Processor 2/26/14 Anthony D. Joseph Blk Y CS 162 ©UCB Spring 2014 Lec 10. 12

Types of Caches • Direct Mapped Cache – Every entry has a direct mapping to it’s place in the cache. If something is mapped to the same place, it gets replaced. • N-Way Set Associative Cache – N-way means that there are n things stored at that cache line. Log (base 2) n from Index added to Tag • Fully Associative Cache – Same as Set Associative except no index bit. Essentially, the number of ways is equal to cache lines.

What Happens on a Write? • Write through: The information is written both to the block in the cache and to the block in the lower-level memory • Write back: The information is written only to the block in the cache. – Modified cache block is written to main memory only when it is replaced – Question is block clean or dirty? • Pros and Cons of each? – WT: » PRO: read misses cannot result in writes » CON: processor held up on writes unless writes buffered – WB: » PRO: repeated writes not sent to DRAM processor not held up on writes » CON: More complex Read miss may require writeback of dirty data 2/26/14 Anthony D. Joseph CS 162 ©UCB Spring 2014 Lec 10. 14

Translation Lookaside Buffer (TLB) • Essentially, a cache for the Page Table • Fixed number of slots containing Page Table Entries meaning you don’t have to go into memory for the Entry. • Nowadays, done in parallel with cache! As long as the offset size is the same. • For Context Switches, must invalidate all of TLB’s entries.