Wafer Cut and Rotation to Improve the Compound

Wafer Cut and Rotation to Improve the Compound yield for 3 D Waferon-Wafer Stacking Bei Zhang Thesis Advisor: Dr. Vishwani D. Agrawal Thesis Committee: Dr. Victor Nelson Dr. Adit Singh Dr. Charles Stroud Department of Electrical and Computer Engineering Auburn University, AL 36849 USA

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 2

Introduction l What’s 3 D IC? A chip in which two or more layers of active electronic components are integrated horizontally or vertically into a single circuit. Wikipedia: http: //en. wikipedia. org/wiki/Three-dimensional_integrated_circuit Apr. 10, 2013 Bei’s General exam 3

Introduction l 3 D IC basic structure: Through silicon Via (TSV) Apr. 10, 2013 Bei’s General exam 4

Introduction l 3 D Packaging? In 3 D packaging, separate chips are stacked in a single package. However, these chips are not integrated into a single circuit. l 3 D transistor? Apr. 10, 2013 Bei’s General exam 5

Introduction l Why 3 D IC? Ø TSV connect the planar wafer in the vertical direction. This reduces the need for long wires which in turn reduces the delay and power consumption. Ø Heterogeneous integration. Ø Reduced foot-print size, desirable in hand-held devices. Apr. 10, 2013 Bei’s General exam 6

Introduction l 3 D IC fabrication methods: Ø Die on Die stacking (D 2 D) Ø Die on Wafer stacking (D 2 W) Advantages : Higher yield, can stack only known good dies Disadvantages: 1) Hard to handle and stack, Process expensive 2) Low throughput 3) May not applicable to high-end systems Ø Wafer on Wafer stacking (W 2 W) Advantages : 1) Highest throughput 2) Allows for highest TSV density Disadvantages: Low compound stacking yield Apr. 10, 2013 Bei’s General exam 7

Introduction l Why compound yield loss in W 2 W stacking? Apr. 10, 2013 Bei’s General exam 8

Introduction l Wafers versus Layers in 3 D W 2 W stacking M. Taouil, S. Hamdioui, J. Verbree, and E. Marinissen, “On Maximizing the compound yield for 3 D wafer-to-wafer stacked IC, " in Proc. International Test Conf. , 2010, pp. 1 -10. Apr. 10, 2013 Bei’s General exam 9

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 10

Problem Statement • Conditions: • N number of repositories each with K wafers • Fault maps for all wafers based on pre-bond testing • A production size of M 3 D ICs • Objective: • Maximize the overall compound yield OR • Maximize the overall number of good 3 D ICs Apr. 10, 2013 Bei’s General exam 11

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 12

Previous Efforts Ø Exploiting different repository replenishment schemes Ø Exploiting various matching algorithms Ø Exploiting different matching criteria Ø Exploiting more practical defect models Ø Specifically design wafers for matching Apr. 10, 2013 Bei’s General exam 13

Different Repository Schemes v Repository replenish schemes can be: Ø Static Repository • None of the repositories will be replenished until they run out of wafers. Ø Running Repository • Each repository is immediately replenished with a new wafer each time a wafer is selected. M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen, “On Maximizing the compound yield for 3 D wafer-to-wafer stacked IC, " in Proc. International Test Conf. , 2010, pp. 1 -10. Apr. 10, 2013 Bei’s General exam 14

Matching Algorithms v Matching algorithms based on Static repository: Globally greedy matching Iterative matching heuristic Integer linear programming Iterative greedy S. Reda, G. Smith, and L. Smith, “Maximizing the Functional Yield of Wafer-to-Wafer 3 -D Integration, ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1357– 1362, Sept. 2009. 15

Matching Algorithms v Matching algorithms based on Running repository: Ø First in First out 1 (FIFO 1) Ø First in First out n (FIFOn) Ø Best Pair (BP) A general W 2 W matching framework can be found in Taouil’s ITC paper, 2010 16

Matching Criteria v Matching criteria: Ø Maximize matching good dies Ø Maximizing matching bad dies Ø Minimize matching between good and bad dies (UF) 17

More Practical Wafer Maps v Illustration of two different kinds of wafer maps: Uniform Clustered 18

Specifically Designed Wafers v Wafers fabricated with rotational symmetry: Double rotation Fourfold rotation B. Zhang, B. Li, V. D. Agrawal, “Wafer cut and rotation to improve the compound yield for 3 D Wafer-on-Wafer stacking, “ Proc. International Test Conf. , 2013, submitted. E. Singh, “Exploiting Rtational Symmetries for Improved Stacked Yields in W 2 W 3 DSICs, ” in Proc. IEEE 29 th VLSI Test Symposium (VTS), 2011, pp. 32– 37. 19

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 20

Illustration of Our Efforts v A hybrid stacking procedure and a new wafer manipulation method: B. Zhang, B. Li, V. D. Agrawal, “Wafer cut and rotation to improve the compound yield for 3 D Wafer-on-Wafer stacking, “ Proc. International Test Conf. , 2013, submitted. 21

Wafer Cut and Rotation v Common wafer cut into sectors Apr. 10, 2013 Bei’s General exam 22

Wafer Cut and Rotation v Cut rotationally symmetric wafer to sectors: Apr. 10, 2013 Bei’s General exam 23

Wafer Cut and Rotation v Sub-wafers rotation: Apr. 10, 2013 Bei’s General exam 24

Wafer Cut and Rotation v Discussion on the number of cuts: Ø Illustration of Die loss on a wafer Places where no die can be placed Apr. 10, 2013 Bei’s General exam 25

Process Flow Apr. 10, 2013 Bei’s General exam 26

Summary v Different wafer manipulation methods: Names Explanations Basic Two wafers are matched directly Rotation 4 Two wafers can be matched in 4 different ways due to rotational symmetry Rotation 2 Two wafers can be matched in 2 different ways due to rotational symmetry Cut and Rotation 4 (CR 4) Each wafer is cut to 4 sectors and with each sector rotated for matching Cut and Rotation 2 (CR 2) Each wafer is cut to 2 sectors and with each sector rotated for matching Apr. 10, 2013 Bei’s General exam 27

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 28

Experiments v Experiment setup: Ø We consider 200 -mm wafers with edge clearance set as 5 mm. Ø Three types of chips with different die sizes: • Type 1: 31. 8 mm 2, dies per wafer is 804, overall yield is 80. 04%, • Type 2: 63. 4 mm 2, dies per wafer is 436, overall yield is 61. 27% • Type 3: 131. 6 mm 2, dies per wafer is 184, overall yield is 50. 97% 29

Experiments v Experiment setup: Ø A production size of 100, 000 3 D ICs is targeted in all experiments for each type of chips. Ø The running repository based best-pair matching algorithm is utilized in the experiment. Ø Employ Heap structure to speed up the matching process Apr. 10, 2013 Bei’s General exam 30

Defect Model Used 1) Uniform defect model 2) Radial clustered degradation model: Inner core yield Type 1: 88% Type 2: 80% Type 3: 70% Normalized yield versus radius for three types of chips D. Teets, “A Model for Radial Yield Degradation as a Function of Chip Size, ” IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 3, pp. 467– 471, 1996. 31

Comparison of Stacking Procedures on Uniform and Clustered Defect Models v Number of stacked layers: 2 Yield comparison between Basic, Rotation 2, CR 2 for type 3 chip 32

Impact of Cut Number and Rotation Number on Compound Yield v Number of stacked layers: 3 Normalized yield versus repository size for type 3 chips 33

Impact of Total Number of Stacked Layers on Compound Yield v Repository size is set as 50 Normalized yield versus number of stacked layers for type 3 chip 34

Impact of Wafer Yield on Compound Yield v Repository size is set as 50 Normalized yield versus inner core wafer yield for type 3 chip 35

Impact of Production Size on Compound Yield v Repository size : 25 Normalized yield versus production size for type 3 chip 36

Exploit More Defect Models The spatial probability functions used to generate the simulated Wafers. Gray levels correspond to failure probabilities ranging from 0 (white) to 1 (black) G. De. Nicoao, E. Pasquinetti, G. Miraglia, and F. Piccinini, “Unsupervised spatial pattern classification of electrical fail-ures in semiconductor manufacturing, ” in Artif. Neural Net-works Pattern Recognit. Workshop, 2003, pp. 125– 131. 37

Yield Comparison Between Different Stacking Procedures (a) Pattern 1 (b) Pattern 2 (c) Pattern 3 (d) Pattern 4 (e) Pattern 5 (f) Pattern 6 (g) Pattern 7 (h) Pattern 8 (i) Pattern 9 38

Impact of Number of Stacked Layers on Compound Yield (a) Pattern 1 (b) Pattern 2 (c) Pattern 3 (d) Pattern 4 (e) Pattern 5 (f) Pattern 6 (g) Pattern 7 (h) Pattern 8 (i) Pattern 9 39

Impact of Production Size on Compound Yield (a) Pattern 1 (b) Pattern 2 (c) Pattern 3 (d) Pattern 4 (e) Pattern 5 (f) Pattern 6 (g) Pattern 7 (h) Pattern 8 (i) Pattern 9 40

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 41

Repository Pollution (downside of running repository) v Phenomenon: • As the production size increases (large production volume), the compound yield of 3 D stacked IC decreases continuously. v Reasons: • Unattractive wafers remain in the repository for many iterations, occupying space, and in effect reducing the size of the repository in the long run. v General solution: • Need a mechanism to force the unattractive wafers to leave the repository in a timely manner. M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen, “On Maximizing the compound yield for 3 D wafer-to-wafer stacked IC, " in Proc. International Test Conf. , 2010, pp. 1 -10. Apr. 10, 2013 Bei’s General exam 42

Repository Pollution (downside of running repository) v Possible detailed solutions: Ø Conduct running repository based matching and static repository based matching, alternatively. Ø Expunge poor wafers/quadrants from the repository if they have not been used after n tries, send them to a die stacking process to make some use of them Ø Exploiting a mechanism to force the unattractive wafer leave the repository at the same rate as they come in. Ø Utilize partial repository instead of running repository to reduce pollution and also enhance the compound yield. Apr. 10, 2013 Bei’s General exam 43

Find Optimal Number of Cuts (Current research is exploring this aspect) v In case of more than 4 cuts, two methods of placement: Placement method 1 Apr. 10, 2013 Placement method 2 Bei’s General exam 44

# of Dies Per Sector (DPS) Calculator v Placement method 1: Apr. 10, 2013 Bei’s General exam 45

# of Dies Per Sector (DPS) Calculator v Placement method 2: Apr. 10, 2013 Bei’s General exam 46

Relationship Between DPW and # of Cuts --- Case Study v # of Type 1 dies per wafer: DPW V. S. number of cuts for placement method 1 and 2 47

Relationship Between DPW and # of Cuts --- Case Study v # of Type 2 dies per wafer: DPW V. S. number of cuts for placement method 1 and 2 48

Relationship Between DPW and # of Cuts --- Case Study v # of Type 3 dies per wafer: DPW V. S. number of cuts for placement method 1 and 2 49

Typical Die Size http: //www. geek. com/glossary/die-size/ Apr. 10, 2013 Bei’s General exam 50

Comparison Between Two Placement Methods – Case Studies v 12 -inch wafer (# of cuts range from 4 to 8): The dots show the cases where method 1 outperforms method 2 Apr. 10, 2013 Bei’s General exam 51

Comparison Between Two Placement Methods – Case Studies v 18 -inch wafer (# of cuts range from 4 to 8): : The dots show the cases where method 1 outperforms method 2 Apr. 10, 2013 Bei’s General exam 52

Presentation Outline v v Introduction Problem Statement Previous efforts Our efforts Ø Proposed a hybrid wafer stacking procedure Ø Proposed a new wafer manipulation method Ø Exploited more defect models Ø Die per sector calculator v Experimental results v Future work Ø Pollution elimination Ø Find the optimal number of cuts v Conclusion Apr. 10, 2013 Bei’s General exam 53

Conclusion Ø Deal with the problem of low compound yield in W 2 W stacking Ø Proposes a hybrid W 2 W stacking scheme Ø Proposes wafer Cut and Rotation manipulation method for yield improvement Ø Extensive experimental results validate the cut and rotation method Ø Develop the die per sector calculator Ø Need to solve repository pollution Ø Need to find the optimal number of cuts Apr. 10, 2013 Bei’s General exam 54

References [1] R. Beica, C. Sharbono, and T. Ritzdorf, “Through Silicon Via Copper Electrodeposition for 3 D Integration, ” in Proc. 58 th Electronic Components and Technology Conference (ECTC), 2008, pp. 577– 583. [2] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer, 2000. [3] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3 D ICs: The Pros and Cons of Going Vertical, ” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498– 510, 2005. [4] G. De. Nicoao, E. Pasquinetti, G. Miraglia, and F. Piccinini, “Unsupervised spatial pattern classification of electrical fail-ures in semiconductor manufacturing, ” in Artif. Neural Net-works Pattern Recognit. Workshop, 2003, pp. 125– 131. [5] X. Dong and Y. Xie, “System-Level Cost Analysis and Design Exploration for Three. Dimensional Integrated Circuits (3 D ICs), ” in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), 2009, pp. 234– 241. [6] J. Dukovic et al. , “Through-Silicon-Via Technology for 3 D Integration, ” in Proc. IEEE International Memory Workshop (IMW), 2010, pp. 1– 2. [7] A. Gupta, W. A. Porter, and J. W. Lathrop, “Defect Analysis and Yield Degradation of Integrated Circuits, ” IEEE Journal of Solid-State Circuits, vol. 9, no. 3, pp. 96– 102, Mar. 1974. 55

References (contd. . ) [8] H. -H. S. Lee and K. Chak, “Test Challenges for 3 D Integrated Circuits, ” IEEE Design & Test of Computers, vol. 26, no. 5, pp. 26– 35, 2009. [9] H. Liao, M. Miao, X. Wan, Y. Jin, L. Zhao, B. Li, Y. Zhu, and X. Sun, “Microfabrication of Through Silicon Vias (TSV) for 3 D Si. P, ” in Proc. 9 th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2008, pp. 1199– 1202. [10] E. J. Marinissen, “Challenges and Emerging Solutions in Testing TSV-Based 2 1/2 D- and 3 D-Stacked ICs, ” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1277– 1282. [11] J. V. Olmen et al. , “ 3 D Stacked IC Demonstration Using a Through Silicon Via First Approach, ” in Proc. IEEE International Electron Devices Meeting (IEDM), 2008, pp. 1 – 4. [12] F. D. Palma, G. D. Nicolao, G. Miraglia, E. Pasquinetti, and F. Piccinini, “Unsupervised spatial pattern classification of electrical-wafer-sorting maps in semiconductor manufacturing, ” Pattern Recogn. Lett. , vol. 26, no. 12, pp. 1857– 1865, Sept. 2005. [13] M. Puech, J. M. Thevenoud, J. M. Gruffat, N. Launay, N. Arnal, and P. Godinat, “Fabrication of 3 D Packaging TSV Using DRIE, ” in Proc. Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 2008, pp. 109– 114. 56

References (contd. . ) [14] S. Reda, G. Smith, and L. Smith, “Maximizing the Functional Yield of Wafer-to-Wafer 3 -D Integration, ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1357– 1362, Sept. 2009. [15] A. Rogers, Statistical Analysis of Spatial Dispersions. United Kingdom: Pion Limited, 1974. [16] E. Singh, “Exploiting Rtational Symmetries for Improved Stacked Yields in W 2 W 3 D-SICs, ” in Proc. IEEE 29 th VLSI Test Symposium (VTS), 2011, pp. 32– 37. [17] E. Singh, “Impact of Radial Defect Clustering on 3 D Stacked IC Yield from Wafer to Wafer Stacking, ” in Proc. International Test Conference (ITC), 2012, pp. 1– 7. [18] L. Smith, G. Smith, S. Hosali, and S. Arkalgud, “Yield Considerations in the Choice of 3 D Technology, ” in Proc. International Symposium on Semiconductor Manufacturing (ISSM), 2007, pp. 1– 3. [19] C. H. Stapper, “On Yield, Fault Distributions, and Clustering of Particles, ” IBM Journal of Research and Development, vol. 30, no. 3, pp. 326– 338, 1986. [20] C. H. Stapper, “Simulation of Spatial Fault Distributions for Integrated Circuit Yield Estimations, ” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 12, pp. 1314– 1318, Dec. 1989. [21] M. Taouil and Hamdioui, “Yield Improvement for 3 D Wafer-to-Wafer Stacked Memories, ” Journal of Electronic Testing: Theory and Applications, vol. 28, no. 4, pp. 523– 534, Aug. 2012. 57

References (contd. . ) [22] M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen, “On Maximizing the Compound Yield for 3 D Wafer-to-Wafer Stacked ICs, ” in Proc. IEEE International Test Conference (ITC), 2010, pp. 1– 10. [23] D. Teets, “A Model for Radial Yield Degradation as a Function of Chip Size, ” IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 3, pp. 467– 471, 1996. [24] J. Verbree, E. J. Marinissen, P. Roussel, and D. Velenis, “On the Cost-Effectiveness of Matching Repositories of Pre-Tested Wafers for Wafer-to-Wafer 3 D Chip Stacking, ” in Proc. 15 th IEEE European Test Symposium (ETS), 2010, pp. 36– 41. [25] T. Yanagawa, “Influence of Epitaxial Mounds on the Yield of Integrated Circuits, ” Proceedings of the IEEE, vol. 57, no. 9, pp. 1621– 1628, Sept. 1969. [26] T. Yanagawa, “Yield Degradation of Integrated Circuits Due to Spot Defects, ” IEEE Transactions on Electron Devices, vol. 19, no. 2, pp. 190– 197, 1972. [27] B. Zhang, B. Li, V. D. Agrawal, “Wafer cut and rotation to improve the compound yield for 3 D Wafer-on-Wafer stacking, “ Proc. International Test Conf. , 2013, submitted. [28] B. Zhang and V. D. Agrawal, “Wafer cut and rotation for compound yield improvement in 3 D Wafer-on-Wafer stacking, ” Proc. 22 nd North Atlantic Test Workshop, 2013. 58

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Thank You! Questions? 60