VME Bus error A possible error condition for
VME Bus error A possible error condition for TMB whose firmware has been “misloaded” is to cause Bus Error on VME crate controller (VCC) at power up… Under these conditions, VCC hangs on first command “because of Rule 2. 35 ‘The Master MUST NOT drive DSA* low until both DTACK* and BERR* are high. ’” (OSU) Able to program TMB mezzanine PROMs if clock removed from system (i. e. , CCB pulled out of crate) Rice does not like this solution OSU would like to test VCC functionality with BERR mask, except no longer any TMB with this problem Going to try to reproduce at Rice by programming TMB 100 times… … In the meantime, verify TMB firmware in CERN software. Compare program shifted out (programmed) bit-by-bit with program shifted in (desired) • If all bits match • software loads program onto the FPGA via hard reset by CCB • else • the software does NOT hard reset • outputs an error message to screen
TMB firmware verify through bootstrap register (JTAG) Snippet from logfile of processing. xsvf file (written from original. mcs files with Impact): Going to define address XSIR -> 38 bits, TDI value = 0 x 3 febffffff XRUNTEST -> XSDRSIZE -> XTDOMASK -> XSDRTDO -> XRUNTEST -> XSIR -> XRUNTEST -> XSDRSIZE -> XTDOMASK -> XSDRTDO -> 2 u. Sec 20 bits, mask = 0 x 000000 20 bits, TDI value = 0 x 000800 Address 20 bits, TDO expected = 0 x 000000 14001 u. Sec 38 bits, TDI value = 0 x 3 feaffffff 0 u. Sec Here comes program 38 bits, TDI value = 0 x 3 fedffffff 2 u. Sec 4100 bits, mask = 0 x 000000000000000000000… 4100 bits, TDI value = 0 x 00000030 c 00006180000 c 30006102000 c 21 c 0 … 4100 bits, TDO expected = 0 x 000000000000000000000… } If “verify” option is selected when writing. xsvf file, the following commands take place for each address (after the prom has been written with above commands): XSIR -> XSDRSIZE -> XTDOMASK -> XSDRTDO -> 38 8196 bits, bits, TDI value = 0 x 3 fefffffff Request to shift out program mask = 0 x 07 ffffffffffffffffffff … TDI value = 0 x 000000000000000000000… TDO expected = 0 x 00000030 c 00006180000 c 30006102000 c 21 c 0 … In program, require: (TDO read-out & mask) = (TDO expected & mask) for every bit
CLCT layer trigger 07/10/2007 TMB firmware. Configuration used: – clct_pretrig_enable = 1 • since it is a “pattern trigger” – layer_trig_enable = 1 – layer_trig_thresh = 2 • 2 comparator layers above threshold in any 1 bx – clct_halfstrip_pretrig_thresh = 7 • disable normal CLCTs – clct_pattern_thresh = 1 • allow layer trigger decision to happen in single bx N. B. layer trigger ~ 0. 2 -0. 3 bx faster than “normal” CLCT pattern trigger… (don’t know why? )
TMB counters with CLCT layer trigger Quick notes: • match trigger rate ALCT trigger rate • Total rate ~1300 Hz, may go to 2600 Hz w/ALCT layer trigger? (N. B. “normal” coincidence rate 300 Hz) • invalid pattern after drift 0
To do: 1. n-layer trigger • Does rate change with layer_trig_thresh? • ALCT (needs firmware download) • ALCT * CLCT 2. Synchronize CSC by pulsing 3. update CMS software with: • VME registers with respect to latest TMB firmware updates • broadcast ALCT firmware broadcast TMB firmware now disabled • Request to resurrect ALCT “Fast self-test” (? ) 4. Write talk for TWEPP-07
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