VLSI Testing Lecture 9 Delay Test n n

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VLSI Testing Lecture 9: Delay Test n n n Delay test definition Circuit delays

VLSI Testing Lecture 9: Delay Test n n n Delay test definition Circuit delays and event propagation Path-delay tests § § § n n Path-delay fault (PDF) and other fault models Test application methods § § n n n Non-robust test Robust test Five-valued logic and test generation Combinational, enhanced-scan and normal-scan Variable-clock and rated-clock methods At-speed test Timing design and delay test Summary Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 1

Delay Test Definition n A circuit that passes delay test must produce correct outputs

Delay Test Definition n A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. Delay test problem for asynchronous circuits is complex and not well understood. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 2

Digital Circuit Timing Input Signal changes Synchronized With clock Copyright 2001, Agrawal & Bushnell

Digital Circuit Timing Input Signal changes Synchronized With clock Copyright 2001, Agrawal & Bushnell Outputs Comb. logic Transient region Inputs Output Observation instant Lecture 9: Delay Test time Clock period 3

Circuit Delays n Switching or inertial delay is the interval between input change and

Circuit Delays n Switching or inertial delay is the interval between input change and output change of a gate: § § § n Propagation or interconnect delay is the time a transition takes to travel between gates: § § n Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs. See Section 5. 3. 5 for timing models. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 4

Event Propagation Delays Single lumped inertial delay modeled for each gate PI transitions assumed

Event Propagation Delays Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P 1 1 0 1 3 P 2 0 3 2 0 Copyright 2001, Agrawal & Bushnell 1 2 4 6 P 3 5 2 Lecture 9: Delay Test 5

Circuit Outputs n n Each path can potentially produce one signal transition at the

Circuit Outputs n n Each path can potentially produce one signal transition at the output. The location of an output transition in time is determined by the delay of the path. Clock period Final value Initial value Slow transitions Fast transitions time Initial value Copyright 2001, Agrawal & Bushnell Final value Lecture 9: Delay Test 6

Singly-Testable Paths (Non-Robust Test) n n The delay of a target path is tested

Singly-Testable Paths (Non-Robust Test) n n The delay of a target path is tested if the test propagates a transition via path to a path destination. Delay test is a combinational vector-pair, V 1, V 2, that: § § don’t care V 1 V 2 Produces a transition at path input. Produces static sensitization -- All off-path inputs assume non-controlling states in V 2. Off-path inputs V 1 V 2 Target path Static sensitization guarantees a test when the target path is the only faulty path. The test is, therefore, called non-robust. It is a test with minimal restriction. A path with no such test is a false path. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 7

Robust Test n n A robust test guarantees the detection of a delay fault

Robust Test n n A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths. A robust test is a combinational vector-pair, V 1, V 2, that satisfies following conditions: n n Produce real events (different steady-state values for V 1 and V 2) on all on-path signals. All on-path signals must have controlling events arriving via the target path. A robust test is also a non-robust test. Concept of robust test is general – robust tests for other fault models can be defined. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 8

Robust Test Conditions n n Real events on target path. Controlling events via target

Robust Test Conditions n n Real events on target path. Controlling events via target path. V 1 V 2 U 1 V 2 S 1 U 1/R 1 V 2 Copyright 2001, Agrawal & Bushnell U 0/F 0 S 0 U 0/F 0 V 1 V 2 S 0 S 1 U 0/F 0 V 1 V 2 U 0 U 1/R 1 U 0/F 0 Lecture 9: Delay Test U 1/R 1 9

A Five-Valued Algebra n n n Signal States: S 0, U 0 (F 0),

A Five-Valued Algebra n n n Signal States: S 0, U 0 (F 0), S 1, U 1 (R 1), XX. On-path signals: F 0 and R 1. Off-path signals: F 0=U 0 and R 1=U 1. Input 1 S 0 U 0 S 1 U 1 XX S 0 S 0 S 0 U 0 U 0 S 1 U 1 XX NOT S 0 U 1 U 1 XX S 0 U 0 XX XX XX S 0 U 0 S 1 U 1 XX OR Input 2 AND Input 1 S 0 U 0 S 1 U 1 XX Input S 0 U 0 S 1 U 1 XX S 1 U 1 S 0 U 0 XX Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test S 0 U 0 S 1 U 1 XX S 1 U 1 XX S 1 S 1 U 1 XX Ref. : Lin-Reddy IEEETCAD-87 10

Robust Test Generation Test for ↓ P 3 – falling transition through path P

Robust Test Generation Test for ↓ P 3 – falling transition through path P 3: Steps A through E E. Set input of AND gate to S 0 to justify S 0 at output XX S 0 U 0 C. F 0 interpreted as U 0; propagates through AND gate U 0 R 1 A. Place F 0 at path origin Path P 3 F 0 XX U 0 D. Change off-path input to S 0 to Propagate R 1 through OR gate F 0 R 1 B. Propagate F 0 through OR gate; also propagates as R 1 through NOT gate Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test Robust Test: S 0, F 0, U 0 11

Non-Robust Test Generation Fault ↑ P 2 – rising transition through path P 2

Non-Robust Test Generation Fault ↑ P 2 – rising transition through path P 2 has no robust test. C. Set input of AND gate to propagate R 1 to output XX U 1 D. R 1 non-robustly propagates through OR gate since off. R 1 path input is not S 0 R 1 Path P 2 A. Place R 1 at path origin U 1 R 1 U 0 XX U 0 B. Propagate R 1 through OR gate; interpreted as U 1 on off-path signal; propagates as U 0 through NOT gate Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test Non-robust test requires Static sensitization: S 0=U 0, S 1=U 1 Non-robust test: U 1, R 1, U 0 12

Path-Delay Faults (PDF) n n Two PDFs (rising and falling transitions) for each physical

Path-Delay Faults (PDF) n n Two PDFs (rising and falling transitions) for each physical path. Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e. g. , Primetime from Synopsys), must be tested. PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests. Three types of PDFs (Gharaybeh, et al. , JETTA, 1997): § § § n Singly-testable PDF – has a non-robust or robust test. Multiply-testable PDF – a set of singly untestable faults that has a non-robust or robust test. Also known as functionally testable PDF. Untestable PDF – a PDF that is neither singly nor multiply testable. A singly-testable PDF has at least one single-input change (SIC) non-robust test. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 13

Other Delay Fault Models n n Segment-delay fault – A segment of an I/O

Other Delay Fault Models n n Segment-delay fault – A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty. Transition fault – A segment-delay fault with segment of unit length (single gate): § § § n n Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-torise transition fault. Models spot (or gross) delay defects. Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates. Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 14

Slow-Clock Test Combinational circuit Input latches Input test clock Test clock period Rated clock

Slow-Clock Test Combinational circuit Input latches Input test clock Test clock period Rated clock period Output latches Output test clock Input test clock Output test clock V 1 applied V 2 applied Output (Launch) latched (Capture) Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 15

Enhanced-Scan Test CK period Combinational PO CK circuit CK TC HL HL HOLD SFF

Enhanced-Scan Test CK period Combinational PO CK circuit CK TC HL HL HOLD SFF V 1 settles SFF SCANIN CK TC CK: system clock TC: test control HOLD: hold signal SFF: scan flip-flop HL: hold latch Copyright 2001, Agrawal & Bushnell Scanout result TC Scanin V 1 states V 1 PI applied Lecture 9: Delay Test Scan mode Scanin V 2 states Normal mode SCANOUT Normal mode PI Result latched V 2 PI Capture applied Launch 16

Normal-Scan Test V 2 states generated, (A) Launch-off-shift (LOS), by one-bit scan shift of

Normal-Scan Test V 2 states generated, (A) Launch-off-shift (LOS), by one-bit scan shift of V 1, or (B) Launch-off-capture (LOC), by V 1 applied in functional mode. Combinational V 1 PIs applied PO Scanin V 1 states circuit SCANOUT CK TC Slow clock SFF SCANIN TC (A) LOS Copyright 2001, Agrawal & Bushnell Path tested Result scanout Rated CK period Scan mode Slow CK period CK TC CK: system clock TC: test control SFF: scan flip-flop Gen. V 2 states Normal mode PI Launch V 2 PIs applied Capture Result latched TC (B) Scan mode LOC Lecture 9: Delay Test Normal mode Scan mode 17 t

Variable-Clock Sequential Test Off-path flip-flop PI PI PI 0 T 1 T n-2 1

Variable-Clock Sequential Test Off-path flip-flop PI PI PI 0 T 1 T n-2 1 PO PI PI T n+1 T n+m PO PO 1 T n-1 2 PO PI PO Initialization sequence (slow clock) 1 Tn 1 2 2 0 D PO Path activation (rated Clock) Fault effect propagation sequence (slow clock) Note: Slow-clock makes the circuit fault-free in the presence of delay faults. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 18

Variable-Clock Models n Fault effect propagation can be affected by ambiguous states of off-path

Variable-Clock Models n Fault effect propagation can be affected by ambiguous states of off-path flip-flops at the end of the rated-clock time-frame (Chakraborty, et al. , IEEETCAD, Nov. 1997): § § § n Fault model A – Off-path flip-flops assumed to be in correct states; sequential non-robust test (optimistic). Fault model B – Off-path flip-flops assumed to be in unknown state; sequential robust test (pessimistic). Fault model C – Off-path flip-flops in steady (hazard-free) state retain their correct values, while others assume unknown state; sequential robust test. Test length: A test sequence of N vectors is repeated N times, with a different vector applied at rated-clock each time. § Test time ~ N 2 x (slow-clock period) Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 19

Variable-Clock Example n n n ISCAS’ 89 benchmark s 35932 (non-scan). 2, 124 vectors

Variable-Clock Example n n n ISCAS’ 89 benchmark s 35932 (non-scan). 2, 124 vectors obtained by simulator-selection from random vectors (Parodi, et al. , ITC-98). PDF coverage, 26, 228/394, 282 ~ 6. 7% Longest tested PDF, 27 gates; longest path has 29 gates. Test time ~ 4, 511, 376 clocks. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 20

Rated-Clock Sequential Test n n n All vectors are applied with rated-clock. Paths are

Rated-Clock Sequential Test n n n All vectors are applied with rated-clock. Paths are singly and multiply activated potentially in several time-frames. Test generation requires a 41 -valued logic (Bose, et al. , IEEETVLSI, June 1998). Test generation is extremely complex for non-scan circuits (Bose and Agrawal, ATS-95). Fault simulators are effective but work with conservative assumptions (Bose, et al. , IEEETVLSI, Dec. 1993; Parodi, et al. , ITC-98). Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 21

Comparing PDF Test Modes Untestable PDFs (False paths) Combinationally testable PDFs testable by variableclock

Comparing PDF Test Modes Untestable PDFs (False paths) Combinationally testable PDFs testable by variableclock seq. test All PDFs of seq. circuit PDFs testable by rated-clock seq. test Ref. : Majumder, et al. , VLSI Design - 98 Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 22

At-Speed Test n n n At-speed test means application of test vectors at the

At-Speed Test n n n At-speed test means application of test vectors at the ratedclock speed. Two methods of at-speed test. External test: § § n Vectors may test one or more functional critical (longest delay) paths and a large percentage (~100%) of transition faults. High-speed testers are expensive. Built-in self-test (BIST): § § Hardware-generated random vectors applied to combinational or sequential logic. Only clock is externally supplied. Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail. Some circuits have initialization problem. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 23

Timing Design & Delay Test n Timing simulation: n n Critical paths are identified

Timing Design & Delay Test n Timing simulation: n n Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). Timing or circuit-level simulation using designer-generated functional vectors verifies the design. Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 24

Summary n n n Path-delay fault (PDF) models distributed delay defects. It verifies the

Summary n n n Path-delay fault (PDF) models distributed delay defects. It verifies the timing performance of a manufactured circuit. Transition fault models spot delay defects and is testable by modified stuck-at fault tests. Variable-clock method can test delay faults but the test time can be long. Scan testing allows two options: n n Launch off shift (LOS) Launch off capture (LOC) Critical paths of non-scan sequential circuits can be effectively tested only by rated-clock tests. Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation: § § § Suppression of non-functional path activation in BIST. Difficulty of rated-clock PDF test generation. Long sequences of variable-clock tests. Copyright 2001, Agrawal & Bushnell Lecture 9: Delay Test 25