VLSI SP Course 2001 Multirate Processing of Digital

VLSI SP Course 2001 Multirate Processing of Digital Signals: Fundamentals For NTUEE VLSI Signal Processing Course Instructor: 吳安宇教授 台大電機吳安宇

VLSI SP Course 2001 Outline • • • Introduction Sampling Rate Conversion Multistage Implementation Practice Structure Polyphase Implementation 台大電機吳安宇

VLSI SP Course 2001 Motivation • Definition – More than one sampling rate (clock) are used in a system Module 1 ? Module 2 clock 1 clock 2 台大電機吳安宇

VLSI SP Course 2001 Conversion Approach • Analog approach • Digital approach (multirate DSP system) 台大電機吳安宇

VLSI SP Course 2001 Analog Approach Advantages Simple Straightforward Arbitrary sampling rate Disadvantages D/A & A/D converter are needed Ideal (near perfect) lowpass filter is needed Introduced noise and distortion 台大電機吳安宇

VLSI SP Course 2001 Digital Approach • Sampling rate conversion – Interpolation • Increase the sampling rate – Decimation • Decrease the sampling rate 台大電機吳安宇

VLSI SP Course 2001 Sampling Theory • If the highest frequency component in a signal is fmax, then the signal should be sampled at the rate of at least 2 fmax for the samples to describe the signal completely, i. e. , For Fs < 2 fmax, alias occurs in the sampling process. Alias Distortion (aliasing) 台大電機吳安宇

VLSI SP Course 2001 Aliasing X(f) f -Fs fmax Fs 台大電機吳安宇

VLSI SP Course 2001 Interpolation by L L h(m) 台大電機吳安宇

VLSI SP Course 2001 Interpolation by L L h(m) 台大電機吳安宇

VLSI SP Course 2001 Decimation by M h(m) M 台大電機吳安宇

VLSI SP Course 2001 Decimation by M h(m) M 台大電機吳安宇

VLSI SP Course 2001 Conversion by a Rational Factor M/L Cascade of two process L h 1(m) Interpolation by L h 2(m) M Decimation by M 台大電機吳安宇

VLSI SP Course 2001 Conversion by a Rational Factor M/L A more efficiency implementation L h (m) M 台大電機吳安宇

VLSI SP Course 2001 Multistage Implementation L L 1 h(m) L 2 h 1(m) LI L 2 h 2(m) h(m) L 1 h 1(m) 台大電機吳安宇

VLSI SP Course 2001 Multistage Implementation Advantages Reduce the complexity Reduce storage devices (registers) Simplify (relax) filter design problem Reduce the finite wordlength effect Disadvantages Increase the control circuit Difficulty in choosing I and best Lj for 1 i I 台大電機吳安宇

VLSI SP Course 2001 Interpolated FIR (IFIR) Approach Nothing to do with interpolation and decimation Conceptually similar Suitable for narrowband FIR filter design LPF HPF BPF 台大電機吳安宇

VLSI SP Course 2001 Application: Interpolated FIR (IFIR) Desired narrowband response Assume required filter order is N. Stretched filter Required filter order is reduced to N/2. Desired Undesired Interpolated version of stretched filter Required filter order is still N/2. Image suppresser Required filter order is M. Order (N/2+M) is needed to implement! (N/2+M) << N for small M 台大電機吳安宇

VLSI SP Course 2001 Interpolated FIR (IFIR) (a) G(z 2) (b) I(z) (a) G(z 2)I(z) 台大電機吳安宇

VLSI SP Course 2001 Interpolated FIR (IFIR) IFIR Method Quantity Compared Conventional Method G(z) I(z) Total Filter order 233 131 6 268 Number of Multipliers 117 66 4 70 Number of Adders 233 131 6 137 台大電機吳安宇

VLSI SP Course 2001 Some Useful Operations Duality and Transposition A dual system is that performs a complementary operation to that of an original system, and it can be constructed form the original system through the process of transposition. The transposition operation is one in which the direction of all branches in the network are reversed, and the roles of the input and output of the network are interchanged. 台大電機吳安宇

VLSI SP Course 2001 Duality and Transposition transposition z-1 z-1 z-1 台大電機吳安宇

VLSI SP Course 2001 Duality and Transposition They are not true in time-varying system, but can be treated as sampling rate reverse process. transposition L L transposition M M transposition h(n) M transposition L h(n) M 台大電機吳安宇

VLSI SP Course 2001 Practical Structure Decimation h(n) M z-1 M z-1 M z-1 M M 台大電機吳安宇

VLSI SP Course 2001 Practical Structure Interpolation L h(n) L L z-1 z-1 z-1 L 台大電機吳安宇

VLSI SP Course 2001 Application: Polyphase FIR Filter Polyphase decomposition E 0(z. M) z-1 E 1(z. M) h(n) z-1 EM-1(z. M) 台大電機吳安宇

VLSI SP Course 2001 Polyphase FIR Filter Noble identity E (z. M) M M E (z) L Noble identity L E (z. M) 台大電機吳安宇

VLSI SP Course 2001 Polyphase FIR Filter E 0(z 3) H (z) 3 z-1 3 E 1(z 3) z-1 h 0 z-1 z-1 E 2(z 3) 3 h 0 h 1 z-3 h 2 z-1 h 3 h 1 h 3 z-1 3 h 4 z-1 h 4 h 2 z-1 h 5 z-3 h 5 台大電機吳安宇

VLSI SP Course 2001 Polyphase FIR Filter E 0(z 3) 3 z-1 3 E 0(z) 3 E 1(z) 3 E 2(z) z-1 E 1(z 3) 3 z-1 E 2(z 3) h 0 z-3 z-1 z-1 3 h 5 3 z-1 3 h 1 z-1 h 4 h 2 h 0 3 3 h 1 z-3 3 h 4 h 2 3 z-1 h 5 台大電機吳安宇

VLSI SP Course 2001 Structure Comparison 3 z-1 3 z-1 3 h 0 3 h 1 z-1 h 2 z-1 h 1 3 h 3 z-1 h 4 Direct implementation h 4 h 2 3 h 5 h 3 z-1 h 5 Polyphase implementation 台大電機吳安宇