VLSI Physical Design Automation Detailed Routing III Prof

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VLSI Physical Design Automation Detailed Routing (III) Prof. David Pan dpan@ece. utexas. edu Office:

VLSI Physical Design Automation Detailed Routing (III) Prof. David Pan dpan@ece. utexas. edu Office: ACES 5. 434 12/4/2020 1

Channel/Switch Box Routing Algorithm a Graph theory based algorithm Yoshimura and Kuh a Greedy

Channel/Switch Box Routing Algorithm a Graph theory based algorithm Yoshimura and Kuh a Greedy algorithm Rivest and Fiduccia a Maze routing and its variations Lee, Robin, Soukup, Ohtsuki a Hierarchical wire routing Burstein and Pelavin 12/4/2020 Channel routing Channel / switchbox and general area routing 2

Over-the-Cell Routing • Channel width can be reduced if some nets can be routed

Over-the-Cell Routing • Channel width can be reduced if some nets can be routed outside the channel. • The metal layers available over the cell rows can be used for routing. (It is possible due to the limited use of the M 2 metal layer within the cells. ) • Commonly used in standard-cell design. 12/4/2020 3

Two-Layer Over-the-Cell Router “Over-the-Cell Channel Routing”, J. Cong and C. L. Liu, TCAD, pages

Two-Layer Over-the-Cell Router “Over-the-Cell Channel Routing”, J. Cong and C. L. Liu, TCAD, pages 408 -418, 1990. 12/4/2020 4

Boundary Terminal Model (BTM) Terminal Rows VDD GND 12/4/2020 5

Boundary Terminal Model (BTM) Terminal Rows VDD GND 12/4/2020 5

The Routing Problem • Boundary Terminal Model (BTM) • Two routing layers in the

The Routing Problem • Boundary Terminal Model (BTM) • Two routing layers in the channel. • One routing layer for over-the-cell routing, so the routing must be planar. 1 2 1 5 2 5 4 3 5 2 1 4 1 5 3 6 5 6 3 3 12/4/2020 6

Hyper-terminal A Hyper-terminal is a set of terminals connected by overthe-cell wires. Hyper-terminals: {A,

Hyper-terminal A Hyper-terminal is a set of terminals connected by overthe-cell wires. Hyper-terminals: {A, C}, {B}, {D, F, K}, {E}, {G, I}, {H}, {J} A B C D E F G H I J K 1 2 1 5 2 5 4 3 5 2 1 4 1 5 3 6 5 6 3 3 L M N O P Q R S T U V Hyper-terminals: {L}, {M, O}, {N}, {P}, {Q, U, V}, {R, T}, {S} 12/4/2020 7

Three Steps of the Algorithm • Routing over the cells. • Select a net

Three Steps of the Algorithm • Routing over the cells. • Select a net segment from each multi-terminal net to be connected in the channel. • Routing in the channel. 12/4/2020 8

Routing Over the Cells • Reduced to a Multi-Terminal Single-Layer One-Sided Routing Problem (MSOP).

Routing Over the Cells • Reduced to a Multi-Terminal Single-Layer One-Sided Routing Problem (MSOP). • Solved by dynamic programming. 12/4/2020 9

MSOP • The fewer the number of hyper-terminals resulted, the simpler the subsequent channel

MSOP • The fewer the number of hyper-terminals resulted, the simpler the subsequent channel routing problem. • Routing a row of terminals using a single routing layer on one side of the row such that the number of hyperterminals is minimized. ? 1 2 1 5 2 5 4 3 5 Can you give a solution for this instance? 12/4/2020 10

MSOP • Can be solved by dynamic programming. • Consider the sub-problem from column

MSOP • Can be solved by dynamic programming. • Consider the sub-problem from column i to j. Let M(i, j) be the maximum reduction in the number of hyperterminals from i to j. Case 1: M(i, j) = ? ? ? Case 2: M(i, j) = ? ? ? No nets at i or the net is not connected to [i, j] i i+1 j Net p i i+1 12/4/2020 p 1 p 2 j 11

MSOP Case 1: M(i, j) = ? ? ? Case 2: M(i, j) =

MSOP Case 1: M(i, j) = ? ? ? Case 2: M(i, j) = ? ? ? No nets at i or the net is not connected to [i, j] i i+1 j Net p i i+1 p 2 j Putting the two cases together: M(i, j) = ? ? ? 12/4/2020 12

MSOP Algorithm • Let n be the total number of pins on the row.

MSOP Algorithm • Let n be the total number of pins on the row. • MSOP algorithm: For i = 1 to n M(i, i) = 0; For j = ? ? to ? ? For i = ? ? to ? ? Compute M(i, i+j) Return M(1, n) 12/4/2020 13

Runtime of MSOP Let n be the total number of columns. For each (i,

Runtime of MSOP Let n be the total number of columns. For each (i, j), M(i, j) can be found in O(? ) time. There are O(n 2) pairs of (i, j). So: Total time = O(? ) 12/4/2020 14

Selection of Net Segment • Need to determine which terminal within a hyperterminal to

Selection of Net Segment • Need to determine which terminal within a hyperterminal to be used in the subsequent channel routing. 1 1 Pick one out of four 1 1 • Can be transformed to a special spanning forest problem. 12/4/2020 15

Connectivity Graph A weighted multi-graph. Each hyper-terminal is represented by a vertex and each

Connectivity Graph A weighted multi-graph. Each hyper-terminal is represented by a vertex and each net is re-presented by a connected component. Take net 3 as an example: 31 1 2 1 5 2 5 4 3 5 [8, 10] [8, 11] [10, 11] [8, 10] 2 1 4 1 5 3 6 5 6 3 3 1 2 3 4 5 6 7 8 9 10 11 column 12/4/2020 [6, 8] 32 [10, 10] 33 [6, 10] a connected component 16

Minimum Density Spanning Forest Problem (MDSFP) • Want to connect hyper-terminals of the same

Minimum Density Spanning Forest Problem (MDSFP) • Want to connect hyper-terminals of the same net together. • That is, finding a spanning tree for each connected component, or finding a spanning forest for the whole connectivity graph. • The goal is to minimize the channel density. This problem is NP-Complete. • Efficient heuristic is proposed. 12/4/2020 17

Heuristic for MDSFP • For each edge e, let r(e) = d(e)/D, where d(e)

Heuristic for MDSFP • For each edge e, let r(e) = d(e)/D, where d(e) is the density of the interval associated with edge e and D is density of the whole channel. r(e) measures the relative degree of congestion over the interval associated with e. • The heuristics repeatedly removes edges of high r() from the connectivity graph until a spanning forest is obtained. The value of r(e) for each edge e is updated after each removal. 12/4/2020 18

Via Minimization • In VLSI fabrication, the yield is inversely related to the number

Via Minimization • In VLSI fabrication, the yield is inversely related to the number of vias. • Every via has an associated resistance that affects the circuit performance. • The size of a via is usually larger than the width of a wire. As a result, more vias will lead to more routing space. 12/4/2020 19

Two Different Problems • Constrained Via Minimization (CVM) • Unconstrained Via Minimization (UVM) 12/4/2020

Two Different Problems • Constrained Via Minimization (CVM) • Unconstrained Via Minimization (UVM) 12/4/2020 20

Constrained Via Minimization (CVM) • Given a detailed routing solution, minimize the number of

Constrained Via Minimization (CVM) • Given a detailed routing solution, minimize the number of vias by assigning wire segments to different layers. Vias occur only at the turning points. • Also called the Layer Assignment Problem. 1 2 3 4 5 4 0 0 0 2 1 0 0 0 3 5 12/4/2020 21

Unconstrained Via Minimization (UVM) • Minimize the number of vias during routing. Vias can

Unconstrained Via Minimization (UVM) • Minimize the number of vias during routing. Vias can occur anywhere as needed. • Consider an unreserved layer model for routing (both vertical and horizontal wires can be routed on the same layer in each region). 12/4/2020 22

Topological Routing UVM is also known as Topological Routing Geometric Mapping 12/4/2020 23

Topological Routing UVM is also known as Topological Routing Geometric Mapping 12/4/2020 23

CVM and UVM is less popular than CVM since via minimization is usually considered

CVM and UVM is less popular than CVM since via minimization is usually considered secondary. Minimization of channel width, completion of routing, and minimization of total wirelength are considered more important. • Note: modern routers usually will follow “preferred” layers. So via minimization essentially is to minimize the number of “bends”. • We will show CVM just to illustrate some algorithmic aspects of via minimization. 12/4/2020 24

CVM by Reduction to Maximum Cut Problem “Optimal Layer Assignment for Interconnect”, R. Y.

CVM by Reduction to Maximum Cut Problem “Optimal Layer Assignment for Interconnect”, R. Y. Pinter, IEEE Int’l Conf. Circuits and Computers, pages 398 -401, Sept. 1982. 12/4/2020 25

Overview • For two routing layers. • Partition the routing region into clusters such

Overview • For two routing layers. • Partition the routing region into clusters such that no “junction” is of degree more than 3. • The problem can be transformed to finding a maximum cut in a graph. 12/4/2020 26

Cluster Graph Representation 1 2 3 4 5 4 0 0 0 2 1

Cluster Graph Representation 1 2 3 4 5 4 0 0 0 2 1 0 0 0 3 5 Cluster Via 1 S 1 h 1 0 2 3 S 3 4 S 1 S 3 h 7 h 3 S 4 h 1 S 2 S 5 h 2 S 6 h S 7 5 S 4 4 h 3 h 4 h 6 S 2 h 5 2 S 6 1 0 0 12/4/2020 0 0 Cluster Graph 0 8 h 7 S 5 h 8 3 S 7 5 27

Layer Assignment In every cluster, there are only two possible ways to assign layers.

Layer Assignment In every cluster, there are only two possible ways to assign layers. Class C 1: Horizontal wires on layer 1 Vertical wires on layer 2 Class C 2: Horizontal wires on layer 2 Vertical wires on layer 1 12/4/2020 28

Assign Clusters to C 1 and C 2 • If two adjacent clusters are

Assign Clusters to C 1 and C 2 • If two adjacent clusters are in the same class, the via candidates joining them are needed. • If two adjacent clusters are in different classes, the vias candidates joining them are not needed. C 2 Same Class C 2 12/4/2020 Different Classes C 2 C 1 29

Example of Class Assignment C 1 Cluster Graph S 1 S 3 h 7

Example of Class Assignment C 1 Cluster Graph S 1 S 3 h 7 C C 2 h 3 S 4 h 1 S 1 2 S 5 C C 1 2 C S h 1 5 h 2 6 h S 7 8 1 2 S 1 h 1 S 2 0 2 3 S 3 4 h 3 h 4 h 2 S 6 1 0 5 S 4 4 h 6 h 5 0 0 h 7 S 5 h 8 012/4/2020 0 3 S 7 5 Original: 8 vias This solution: 4 vias 30

Example of Class Assignment C 1 S 1 S 3 h 7 C C

Example of Class Assignment C 1 S 1 S 3 h 7 C C 1 h 3 S 4 h 1 S 2 2 S 5 C C 2 1 C S h 2 5 h 2 6 h S 7 A better solution: 8 1 S 1 2 S 2 h 1 0 2 3 S 3 4 5 S 4 h 3 h 2 S 6 1 4 h 6 h 5 0 0 0 h 7 S 5 h 8 3 12/4/2020 Optimal Solution: 2 vias S 7 5 31

Class Assignment Problem No. of vias = No. of via candidates – No. of

Class Assignment Problem No. of vias = No. of via candidates – No. of edges connecting a vertex in C 1 and a vertex in C 2 S 1 S 2 C 1 S 3 S 4 S 7 No. of edges here Optimal Solution = no. of vias that S 1 can be eliminated S 6 S 2 C 1 C 2 S 3 S 5 S 4 12/4/2020 S 7 S 5 32

Maximum Cut Problem • The layer assignment problem is equivalent to the Maximum Cut

Maximum Cut Problem • The layer assignment problem is equivalent to the Maximum Cut Problem of a graph. A cut Maximum cut = A cut with the maximum no. of edges • The Maximum Cut Problem is – NP-Complete for general graphs. – Solvable in polynomial time for planar graphs. [Hadlock 1975, SIAM Journal on Computing] • Cluster graphs are planar. 12/4/2020 33

Other Routing Issues • Gridless Routing • Multi-level routing • DSM effects 12/4/2020 34

Other Routing Issues • Gridless Routing • Multi-level routing • DSM effects 12/4/2020 34

Gridless Detailed Routing • Gridless Routing – More flexible – Longer runtime due to

Gridless Detailed Routing • Gridless Routing – More flexible – Longer runtime due to complex data structure • Gridless Detailed Routing Algorithms – Shape (Tile) based routing [Sato, et al. , ISCS 87, Margarino, et al. , TCAD 87, Dion, et al. , WRL Research Report 95/3, Liu, et al. , ISPD 98] – Graph-based routing [Wu, et al. , TC 87, Ohtsuki, ICCAS 85, Cong, et al. , Zheng, et al. , TCAD 96, ICCAD’ 99] – Subgrid routing [US Patent, 6, 507, 941 B 1, Jan. 2003] 12/4/2020 35

Multilevel Routing Framework (MARS [TCAD 05]) Detailed routing Fine routing tile generation • Implicit

Multilevel Routing Framework (MARS [TCAD 05]) Detailed routing Fine routing tile generation • Implicit graph gridless routing G 0 G 1 Coarsening G 1 Gk Refinement • History-based iterative refinement • Multicommodity flow based algorithm Initial routing [Courtesy Prof. Jason Cong] 12/4/2020 36

DSM Considerations • • • Antenna effects Crosstalk noise Interconnect optimization & planning Manufacturability

DSM Considerations • • • Antenna effects Crosstalk noise Interconnect optimization & planning Manufacturability …… Will be covered in EE 382 V, Optimization Issues in VLSI CAD 12/4/2020 37