VLSI Design Lecture 2 Basic Fabrication Steps and

VLSI Design Lecture 2: Basic Fabrication Steps and Layout Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture notes

Outline n How to make a transistor or a gate v Cross-section v Top view (masks) v Fabrication process n n Layout Design rules Standard cell layouts Stick Diagrams Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 2 of 50

Our technology n We will study a generic 180 nm technology (SCMOS rules). v Assume 1. 2 V supply voltage. n n Parameters are typical values. Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm. Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 3 of 50

Fabrication services n Educational services: v U. S. : MOSIS (has defined SCMOS rules) v EC: Euro. Practice v Taiwan: CIC v Japan: VDEC n Foundry = fabrication line for hire. v Foundries are major source of fab capacity today. Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 4 of 50

Silicon Lattice n n n Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 5 of 50

Dopants n n n Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic, Phosphorus): extra electron (n-type) Group III (Boron): missing electron, called hole (p-type) Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 6 of 50

p-n Junctions n n A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction N-Diff cathode Modern VLSI Design 4 e: Chapter 2 P-Diff anode Sharif University of Technology Slide 7 of 50

Fabrication processes n IC built on silicon substrate: v some structures diffused into substrate; v other structures built on top of substrate. n n n Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (Si. O 2) is insulator. Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 8 of 50

CMOS Fabrication n n CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 9 of 50

CMOS Inverter Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 10 of 50

Inverter Cross-section n n Typically use p-type substrate for n. MOS transistors Requires n-well for body of p. MOS transistors Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 11 of 50

Well and Substrate Taps n n n Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 12 of 50

Inverter Mask Set n n Transistors and wires are defined by masks Cross-section taken along dashed line Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 13 of 50

Detailed Mask Views n Six masks v n-well v Polysilicon v n+ diffusion v p+ diffusion v Contact v Metal Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 14 of 50

Fabrication Steps n n n Start with blank wafer Build inverter from the bottom up First step will be to form the n-well v Cover wafer with protective layer of Si. O 2 (oxide) v Remove layer where n-well should be built v Implant or diffuse n dopants into exposed wafer v Strip off Si. O 2 Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 15 of 50

Oxidation n Grow Si. O 2 on top of Si wafer v 900 – 1200 C with H 2 O or O 2 in oxidation furnace Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 16 of 50

Photoresist n Spin on photoresist v Photoresist is a light-sensitive organic polymer v Softens where exposed to light Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 17 of 50

Lithography n n Expose photoresist through n-well mask Strip off exposed photoresist Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 18 of 50

Etch n Etch oxide with hydrofluoric acid (HF) v Seeps through skin and eats bone; nasty stuff!!! n Only attacks oxide where resist has been exposed Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 19 of 50

Strip Photoresist n Strip off remaining photoresist v Use mixture of acids called piranah etch n Necessary so resist doesn’t melt in next step Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 20 of 50

n-well n n n-well is formed with diffusion or ion implantation Diffusion v Place wafer in furnace with arsenic gas v Heat until As atoms diffuse into exposed Si n Ion Implanatation v Blast wafer with beam of As ions v Ions blocked by Si. O 2, only enter exposed Si Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 21 of 50

Strip Oxide n n n Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 22 of 50

Polysilicon n Deposit very thin layer of gate oxide v < 20 Å (6 -7 atomic layers) n Chemical Vapor Deposition (CVD) of silicon layer v Place wafer in furnace with Silane gas (Si. H 4) v Forms many small crystals called polysilicon v Heavily doped to be good conductor Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 23 of 50

Polysilicon Patterning n Use same lithography process to pattern polysilicon Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 24 of 50

Self-Aligned Process n n Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms n. MOS source, drain, and n-well contact Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 25 of 50

N-diffusion n Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 26 of 50

N-diffusion cont. n n n Historically dopants were diffused Usually ion implantation today But regions are still called diffusion Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 27 of 50

N-diffusion cont. n Strip off oxide to complete patterning step Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 28 of 50

P-Diffusion n Similar set of steps form p+ diffusion regions for p. MOS source and drain and substrate contact Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 29 of 50

Contacts n n n Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 30 of 50

Metalization n n Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 31 of 50

Simple cross section Si. O 2 metal 3 metal 2 metal 1 transistor via poly n+ Modern VLSI Design 4 e: Chapter 2 p+ n+ substrate Sharif University of Technology Slide 32 of 32

Photolithography Mask patterns are put on wafer using photo-sensitive material: Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 33 of 32

Process steps n First place tubs (wells) to provide properly-doped substrate for n-type, p-type transistors. a twin-tub process: p-tub n-tub substrate Modern VLSI Design 4 e: Chapter 2 Sharif University of Technology Slide 34 of 32

Process steps, cont’d. Pattern polysilicon before diffusion regions: poly gate oxide p-tub Modern VLSI Design 4 e: Chapter 2 poly n-tub Sharif University of Technology Slide 35 of 32

Process steps, cont’d Add diffusions, performing self-masking: poly n+ p-tub Modern VLSI Design 4 e: Chapter 2 poly n+ p+ Sharif University of Technology n-tub p+ Slide 36 of 32

Process steps, cont’d Start adding metal layers: metal 1 vias poly n+ p-tub Modern VLSI Design 4 e: Chapter 2 n+ poly p+ Sharif University of Technology n-tub p+ Slide 37 of 32