Vinayak Nagpal ManKit Leung Terry Filiba vnagpal mankit

Vinayak Nagpal, Man-Kit Leung, Terry Filiba { vnagpal, mankit, tfiliba }@eecs. berkeley. edu University of California, Berkeley VHDL Code Generation for Ptolemy II Project Overview 1. 2. 3. PTII Model VHDL Codegen Verification Generate VHDL descriptions for Ptolemy models. Maintain bit and cycle accuracy in implementation. Current work focuses on using a subset of Ptolemy actors in the Synchronous/Reactive (SR) Domain. Motivation Why use Ptolemy to generate VHDL? • HW/SW co-design - Complex embedded systems are increasingly using a combination of software and custom hardware components. The hardware is usually implemented on an FPGA platform while the software is run on an off-the-shelf embedded processor or a softprocessor within the same FPGA. The capability to generate VHDL complements the existing C code generation framework and brings Ptolemy II closer towards facilitating hardware-software codesign where different parts of a system can be designed together and targeted separately to run either in software of hardware. • VHDL is Hard - Most hardware systems (especially in DSP) can be designed structuraly using a small set of high level primitives like counters, multiplexors, adders etc. A graphical interface to describe relations between such primitives is closer to drawing schematics on paper and thus lends easily to intution. Such a design and debugging environment can prove far more accesible to system designers than writing Verilog/VHDL descriptions. Acknowledgements: Ptolemy II Actors We have created Ptolemy VHDL actors that comply with the special semantics of the Synchronous/Reactive domain. The VHDL actors are strictly typed and support only fixed point tokens. These actors also support latencies which implement register chains of user defined length within the actor. This behaviour is emulated by the generated circuit in VHDL. Logic synthesis tools can use this for register retiming hence allowing to meet tighter timing constraints. VHDL Component Library A library of basic hardware building blocks has been designed in VHDL. IEEE has recently introduced support for fixed point arithmetic inherently to VHDL 2006. These facilities are liberally used and provide most arithemetic operations in fixed point with saturation and rounding. support. All blocks of the library are highly parametrizeable. All but some can be synthesized to hardware and have been tested with Synplify FPGA tools. The blocks that do not synthesize are used for special test features. Helper-based Code Generation Prof. Edward Lee, Christopher Brooks, Pierre Droz, Chen Chang A codegen helper is essentially a component that generates code for a Ptolemy II actor. Each Ptolemy II actor class has one associated helper. A helper consists of two files: a java class file and a code template file. The code template file contains code blocks written in the target language. The code template files are hand-coded so users have flexibility their design style and algorithm. Hand-coded templates also retain readability in the generated code. It also contains codegen macros that the codegen kernel will read and performs text substitutions. The macros allows the kernel to achieve some degree of understanding of the content of the code blocks so the kernel knows how to do proper code stitching. The java class of the helper interacts with the codegen kernel to harvest code blocks from the code template file. The helper java class basically contains logic to determine which code block to harvest. The java class of helper can retrieve useful information from its associated PTII actor. The informations usually are actor instance-specific information (i. e. port type, port width, and parameter values). These values act as inputs to the logic of the helper java class for fetching specific code blocks from the code template file. Conclusion • We present an infrastructure for VHDL code generation in Ptolemy II. • The generated VHDL code is bit-cycle accurate as the simulation. Future Work • Code generation for heterogeneous domains, such as Finite State Machine (FSM) and Discrete Event (DE). • Automate interfacing of circuits with external components on the BEE 2 suite of FPGA boards by generating appropriate files used by Xilinx EDK.