VHDL Model Sim CPU Architecture Serge Karabchevsky Objectives

VHDL & Model. Sim CPU Architecture Serge Karabchevsky

Objectives Course Website, Software and Hardware Logic Timing Introduction to VHDL Model. Simulation First Assignment Definitions

Course Website http: //hl 2. bgu. ac. il n n Announcements Assignments Lectures Forums Anyone can ask Anyone can answer (if he knows the answer) Check Google before asking at forum. Reception hours n n n At the forums Monday 1600 -1700 - Scheduling by email Email : serge@ee. bgu. ac. il

Course Software Modelsim (Simulator) n http: //model. com/content/modelsim-pe-student -edition-hdl-simulation Quartus (FPGA Compiler) n http: //www. altera. com/products/software/quart us-ii/web-edition/qts-we-index. html MARS (MIPS compiler) n http: //courses. missouristate. edu/Ken. Vollmar/ MARS/

Course Hardware Altera DE 1 FPGA Board Cyclone II EP 2 C 20 F 484 C 6 FPGA 50 MHz, 27 MHz and 24 MHz oscillators 4 pushbutton switches 10 toggle switches 10 red LEDS 8 Green LEDs

Logic Timing Tpd : Time from state change at input to state change at output

DFF Timing Tco : Time from clock rise to output state change Tsu : Time that input must be stable before clock rise Th : Time that input must be stable after clock rise

Calculating Frequency Long Path Rule (Setup): 1/FMax = Tco 1+Tpd. Max+Tsu 2+tskew Short Path Rule (Hold): Tco 1+Tpd. Min > Th 2+tskew

Introduction to VHDL Very high speed integrated circuits Hardware Description Language Entities Architectures n n n Structural Dataflow Behavioral (Process , examples) Test Bench Generic Variables Generate Loops Packages and Simulating Delays

VHDL Design must have a top level entity with : n n n At least one input (test-bench is an exception) At least one output (test-bench is an exception) Optional Parameter (generic variable) Each entity is located in separate file File is with. VHD extension

VHD File Structure -- Library Definition library ieee; use ieee. std_logic_1164. all; use IEEE. std_logic_unsigned. all; -- Entity Definition entity counter is port (clk : in std_logic; q : buffer unsigned (7 downto 0)); end entity; -- Architecture Definition architecture rtl of counter is -- Component and signal declaration Begin -- Design Body process (clk) begin if (rising_edge(clk)) then q <= q + 1; end if; end process; end rtl;

An Entity In the Entity we define our design like a black-box with only inputs and outputs. entity_name is generic ( generic_declarations ) ; port ( port_declarations ) ; end entity_name ; entity nand 2 is port ( a, b : in std_logic; c : out std_logic ) ; end nand 2 ; entity xor is generic ( N : integer : = 4 ) ; port ( a : in std_logic_vector(N-1 downto 0); b : out std_logic ) ; end xor ;

Architecture In the Architecture we define the logic of our Entity (contents) and it’s connection to inputs and outputs The types of architecture are : • Structural • Dataflow • Behavioral architecture_name of entity_name is [ component declaration ] [ signal declaration ] begin [ design logic ] end architecture_name ; architecture rtl of nand 2 is begin c <= a NAND b; end rtl ;

Entity and Architecture

Structural Architecture Using existing components (entities) in order to build a new one, like connecting chips each to other All the components must be declared before the architecture begin Then the components are instantiated and connected each to other using signals

Structural AND Gate from NAND and NOT entity and 2 is port ( a, b : in std_logic; c : out std_logic ) ; end and 2 ; architecture struct of and 2 is component nand 2 is port ( a, b : in std_logic; c : out std_logic ) ; end component ; component not_gate is port ( a : in std_logic; b : out std_logic ) ; end component ; signal nand_out : std_logic; begin U 1 : nand 2 port map (a=> a , b=>b, c=> nand_out); U 2 : not_gate port map (a=> nand_out , b=>c); end struct ;

Data Flow Architecture Circuits are described by indicating how the inputs and outputs of built-in primitive components (ex. and gate) are connected. In other words we describe how signals flow through the circuit. entity latch is port (s, r : in std_logic; q, nq : out std_logic); end latch; architecture dataflow of latch is begin q <=r nor nq; nq <=s nor q; end dataflow;

Behavioral Architecture Describes the behavior of components in response to signals. Behavioral descriptions of hardware utilize software engineering practices to achieve a functional model. Timing information may be included for simulations. Requires PROCESS statement

What can be behavioral Combinational Logic n n Simple combinational logic Latches Sequential logic n n n Flip Flop Mix of Combinational logic with Flip-Flops Flip Flops with asynchronous Reset/Preset Test Bench

It is Not a Software Behavioral description describes a Logic , not a software. Be careful of what you are writing. Timing commands can be used only in test bench or for delays definition in simulation. Do not use timing commands to create logic The design should work normally if you remove the timing commands

Process Used for all behavioral descriptions Statements within a process are executed sequentially All processes in a VHDL description are executed concurrently Will be executed (in simulator) in case of state change of at least one signal in PROCESS (sensitivity list) sensitivity list declarations BEGIN Process body (behavioral description) END PROCESS;

Signals SIGNAL a, b : std_logic; Signals are local for specific architecture , they are used for interconnect between different processes and components When assigning a signal in a process it will change only after process completion Only the last assignment counts (including assignments under IF or CASE) If there is no active assignment , signal holds it’s previous state (Latch) Assignment is done by ‘<=‘

Variables Local to the process they are defined A variable behaves like you would expect in a software programming language Assignment takes time immediately Assignment is done by ‘: =‘ VARIABLE tmp : integer range 0 TO 15;

Combinational Description All the process input signals must be in the sensitivity list Signal must have an active assignment in all the paths (if , case …). Otherwise latch will be created A default assignment can be used at the beginning of the process to avoid latches

Combinational Description Example

Common Error

Sequential Description rising_edge statement must present in the process body

Asynchronous reset paths Only one synchronous path Only one Asynchronous path

Test Bench Used to test the design functionality Not translated to real hardware Wraps around the design You can write everything you want (like Software)

How Test Bench Works Input generation DUT Golden Model Output =? observation Golden Output Error Reporting : process(clk) begin if (clk'event and clk='1') then ASSERT out_dut = out_golden REPORT “Test Failed" SEVERITY error; end if; end process; Error Report

Generic variables Compilation Driven Parameters Can’t change at run time entity nand 2 is generic (tpd: time); port ( a, b : in std_logic; c : out std_logic ) ; end nand 2 ; architecture rtl of nand 2 is begin c <= a NAND b after tpd; end rtl ; Instantiation : U 1: nand 2 generic map (tpd => 1 ns) port map (a => a_signal, b=>b_signal , c=>c_signal);

Generate loops entity register is port) reset, clk : in std_logic; d : in std_logic_vector 4)downto 0; ( q: out std_logic_vector 4)downto 0; (( end register; architecture struct of register is component dff port) reset, clk, d : in std_logic; q, q_not : out std_logic; ( end component; begin Array_Of_DFFs : for i in D'range generate dffi : dff port map) reset <=reset, clk => clk, d => d(i), q => q(i; (( end generate; end struct;

Packages Saves time on component declaration , no need for code duplication. sample_package. vhd library IEEE; use IEEE. STD_LOGIC_1164. ALL; PACKAGE sample_package is component nand 2 port(a, b : in std_logic; c : out std_logic; ( end component; component not_gate port(a : in std_logic; b : out std_logic; ( end component; end sample_package; In design files add : use WORK. sample_package. ALL;

Simulating Delays architecture rtl of and 2 is begin c <= a and b after 1 ns; end rtl ; Creating component delay for simulation In The Test bench : All the times are relative to zero a <= ‘ 1’, ‘ 0’ after 2 ns, ‘ 1’ after 7 ns; b <= ‘ 1’, ‘ 0’ after 4 ns, ‘ 1’ after 6 ns; (Start of line execution) a b t[ns] c 0 1 2 3 4 5 6 7 8 9 t[ns]

Model. Simulator Learn By Example

First Example N Bit Register Uses Package Download it from HL and simulate Are there any logic delays?

How to use Model. Sim? Create Project with “work” library (“File->New->Project”) Add files to project (“Project->Add to Project”) Edit. vhd files Set compilation order (“Compile->Compile order”) Compile all the. vhd files (“Compile->Compile All”) Load the “test bench” configuration file. (double-click on the configuration link of the complied test bench in “work” library) Add a new wave window (“View->New Window->Wave”)

How to use Model. Sim? (cont’) Copy the relevant signals to the wave window Run simulation (Simulate->Run) Work the right way… so u won’t loose grade: n n n Change signal names to friendly ones (Display Names) Use “Dividers” between signals Mark time periods Zoom on the right signals Use Hexadecimal notations when necessary Save the wave format to use it later (“File->Save)

Second Example Delay Line Download it from HL and run on your own. Are there any logic delays?

Make Changes on the Second Example Change clock period to 20 n Change delay line depth to 4 Run the simulation again

Good luck! Any questions?