Very low voltage 16 bit counter in high

Very low voltage 16 -bit counter in high leakage static CMOS technology COLIN STEVENS LOW POWER ELECTRONICS ELEC 6270 INSTRUCTOR-VISHWANI D. AGRAWAL

Theory and Simulation . 18µm TSMC process in Design Architect Vth NMOS: . 3725 v / Vth Pmos: -. 3948 |Vtp| + Vtn =. 7673 V 90 ns transient analysis Using ELDO Waveform Viewing in EZWAVE

Counter Selection Asynchronous Advantages Simple Design Utilizes Clock Gating Fast for small counters Disadvantages Ripple Effect Delay Grows with Counter Size Synchronous Advantages No Ripple Effect. Delay of all outputs are equal. Disadvantages More Logic Required Flip Flops are clocked even when no transition is required

Synchronous Counter

EZWAVE Vdd = 1. 2 V

Power, Delay, and Frequency

Log Display and Power Delay Product

Results 90 ns Transient analysis Voltage Power % Reduction from Optimal Voltage (1. 2 V) Delay (ns) % Reduction from Optimal Voltage (1. 2 V) Frequency 1/(delay + 10%) (Mhz) 5 V 5. 1264 m. W -8482. 62% 1. 14 71. 50% 797. 45 4 V 2. 6631 m. W -4358. 56% 1. 19 70. 25% 763. 94 3 V 1. 1481 m. W -1822. 15% 1. 314 67. 15% 691. 85 2 V 0. 28895 m. W -383. 76% 1. 89 52. 75% 481 1. 4 V 90. 81 n. W -52. 03% 3. 18 20. 50% 285. 88 1. 3 V 74. 226 n. W -24. 27% 3. 68 8. 00% 247. 04 1. 2 V 59. 73 n. W 0. 00% 4 0. 00% 227. 27 1. 1 V 48. 232 n. W 19. 25% 5 -25. 00% 181. 82 1 V 39. 629 n. W 33. 65% 7 -75. 00% 129. 87 . 9 V 33. 518 n. W 43. 88% 9 -125. 00% 101. 01 . 77 V 25. 699 n. W 56. 97% 17 -325. 00% 53. 48 . 76 V 25. 503 n. W 57. 30% 19 -375. 00% 47. 85

Sub-threshold Results Voltage Power (n. W) Delay (ns) Frequency 1/(delay + 10%) 0. 6 20. 60 88 10. 33 Mhz 0. 5 2. 07 477 1. 91 Mhz 0. 4 0. 84 3, 640 0. 25 Mhz 0. 34 30, 700 29. 61 Khz 0. 20 245, 000 3. 71 Khz 0. 1 0. 09 1, 880, 000 480 Hz

Optimizations and Conclusions Potential Optimization Low threshold gates could be used along the critical path of and gates to make the circuit faster at lower voltages. Conclusions Tradeoff between power and delay for a given circuit. I would like to have gotten the predictive models to work.

References Agrawal, V. D. (2007). Power Dissipation in CMOS Circuits [Power Point Presentation]. Retrieved from: http: //www. eng. auburn. edu/users/agrawvd/COURSE/E 6270_Spr 09/LECTURES/lpd_4_CMOSPower. ppt Counter. (nd). Retrieved April 15, 2009, from Wikipedia Website: http: //en. wikipedia. org/wiki/Counter Low-power electronics. (nd). Retrieved April 15, 2009, from Wikipedia Website: http: //en. wikipedia. org/wiki/Lowpower_electronics Kulkarni, Vidya (nd). Logic Design Chapter – 5 [Power. Point Presentation]. Retrieved from: forum. vtu. ac. in/~edusat/Prog 5/logd/vrk/Chapter-5. ppt

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