VERTEX DETECTORS FOR FUTURE LINEAR COLLIDERS Mathieu Benoit
VERTEX DETECTORS FOR FUTURE LINEAR COLLIDERS Mathieu Benoit Linear Collider Detector Group (PH-LCD), CERN
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Outline • The future linear collider projects • The Compact Linear Collider (CLIC) • The International Linear Collider (ILC) • Vertex detector requirements in linear colliders • Physics requirements • Impact on vertex detector design • The detector concepts • Si. D and ILD • CLIC_Si. D and CLIC_ILD • Sensor technology • • Depleted Field-Effect-Transistor Pixel Sensors (DEPFET) Fast Pixel Charge-Coupled Device (FPCCD) Monolithic Active Pixel Sensors (MAPS) Silicon-On-Oxide Monolithic Sensor (SOI) • CLIC R&D for vertex detector instrumentation • • Ultra-Thin Hybrid Pixel Assemblies (CLICPix prototypes and Smallpix) Sensor simulation and digitization studies R&D on cooling and mechanical integration Power-Pulsing and power delivery R&D 2
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 3 Future linear collider projects Future linear colliders are e+ e- colliders aiming at performing precision measurements of Standard model (SM) and beyond SM parameters (mass, coupling, Branching ratio, etc …) CLIC ILC • Based on a 2 -beam acceleration scheme • Based on superconducting RF cavities • Gradient : 100 MV/m • Room-Temperature operation • Energy : 3 Te. V, staged approach starting ~250 Ge. V possible • 50 Hz train rate, 156 ns per train, 312 bunches per train, 0. 5 ns bunch separation 20 ms 0. 5 ns bunch separation 156 ns bunch train, 312 bunches per train (not all represented here) (like XFEL) • Gradient : 32 MV • Energy : 500 Ge. V upgradable to 1 Te. V • 5 Hz train rate, 969 ns per train, 2625 bunches per train, 369 ns bunch separation
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Vertex detector requirements in linear colliders • Single-Point Resolution (σsp=3 -5 um) requirements for vertexing and charged particle impulsion measurements Ø Very low sensor thicknesses (~0. 1% per layer, ~100 um of Silicon) to reduce multiple scattering Ø Pixel size ~O (20 x 20 um) Ø Air cooling to reduce inactive material in the vertexing volume • Timing of single hits with a resolution of ~350 ns (ILC) and ~10 ns (CLIC) for reduction of beam background-induced hits • High Granularity to reduce occupancy and reduce probability of double hits • Small pixel size ~O (20 x 20 um) • Low power electronics (~ 2 u. W/channel) 4
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan The ILD vertex detector concept • Material Budget • 0. 11, 0. 16 % Xo for VTX-SL/DL at normal incindence • 500 um overlap between sensitive regions of ladders • Physics Requirements • SPR : < 3 um • Double hit separation : < 40 um • Sensor thickness: ~ 50 um • 4 T magnetic field • Foreseen Technology • CMOS, DEPFET, FPCCD 5
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan The Si. D vertex detector concept • Material Budget • ~0. 1 % X 0 target per layer at normal incidence • Physics Requirements • SPR : < 5 um • Double hit separation : < 40 um • Sensor thickness: ~ 50 -100 um • 5 T magnetic field • Foreseen Technology • 3 D Hybrid , DEPFET, CHRONOPIX 6
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLIC_Si. D and CLIC_ILD The CLIC versions of Si. D and ILD detectors are modified to take into account the different bunch train structure: • Beam pipe pushed at outer radius to avoid high occupancy from beam background • Power consumption must be reduced by means of Power. Pulsing to take advantage of the small duty cycle associated to the beam train structure 7
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Sensor technologies for futures linear colliders : DEPFET • • • The Depleted Field-Effect transistor relies on a depleted layer located under a FET. A Potential minimum is created in the channel of the transistor Accumulation of charge from ionizing particles modified the charge distribution in the channel and increase the Transistor current Monolithic Sensor allow for thin Assembly (50 um , ex: PXD 6) Allows for small pixel size (~25 x 25 um) Integrating sensor (Frame ~25 -100 us), so coarse timestamping • The ultra low mass cooling system of the Belle II DEPFET detector • The Belle II pixel detector: high precision with low material Dr Marinas Pardo, poster session, Oral presentation Session 2 Source : DEPFET active pixel detectors, Marcel Vos – IFIC Valencia, KILC 2012 8
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 9 Sensor technologies for futures linear colliders : FPCCD • Fine Pixel Charge-Coupled Device (5 x 5 um) • A ~15 um depleted region in created in the sensitive area to favorize drift of carrier and limit diffusion • Integrate over a bunch train, readout during gap between trains • Fast-Readout needed (>10 MPixel/s) • No Timestamping, occupancy kept low by small pixel size, background rejected by pattern recognition • To limit power consumption and obtain faster readout, sensor need air cooling at low temperatures ~(-40 C) Source : Developments of Readout ASIC for FPCCD vertex detector, Eriko Kato, Tohoku U. , KILC 2012
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 10 Sensor technologies for futures linear colliders : CMOS Pixel Sensors (MAPS) MIMOSA Family (IPHC) • Monolithic sensor, CMOS process with high-resistivity epitaxial layer to increase signal and limit diffusion • Electronics integrated in pixel • Correlated-Double Sampling (CDS) in pixel • Rolling shutter read-out (coarse timing) • Analog or digital readout possible • Proposed 2 type of sensors for inner and outer layers (PLUME) • MIMOSA-30 : Dual sided readout • 1 side for spatial resolution (16 x 16 um pixel), 1 side for timing (~10 us, 16 x 80 um pixel) • MIMOSA-31 : Larger pixel for reduced power consumption (35 x 35 um) • R&D Ongoing to develop faster-readout, sparsified readout, stiching of sensors , larger depleted area See Session 6 for details on the MAPS technology Source : Towards a Vertex Detector Concept with a Microsecond Timestamping, Marc Winter, IPHC, KILC 2012
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Sensor technologies for futures linear colliders : SOI Pixel Sensors • CMOS sensor on SOI wafers • Fully depleted High-Resistivity sensor • Electronics on low resistivity wafer separated by BOX from sensing layer • Allow for standard CMOS electronics • Fast time stamping possible • Complex pixel « intelligence » • Insulation of each device from bulk allow for low leakage current operation Progress of SOI Pixel Process Yasuo Arai, Session 2 High-Resolution Monolithic Pixel Detectors in SOI Technology Toshinobu Miyoshi, session 4 A thin fully-depleted monolithic pixel sensor in SOI technology Serena Mattiazzo, session 4 3 D Integration for SOI Pixel Detector Makoto Motoyoshi , session 4 Source : Monolithic Pixel Detector with SOI technology, Yasuo Arai, CERN seminar, June 28 th 2011 11
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 12 CLIC R&D for vertex detector instrumentation • Requirements • • • ~ 20 x 20 μm 2 pixel sizes : need small feature sizes ! Time-stamping ~10 ns : need high-resistivity sensor ! ~0. 2% material/layer : corresponds to ~200 μm silicon (incl. support + cables) ! 156 ns bunch train every 20 ms : trigger-less readout, power pulsing ! Magnetic field 4 -5 T : Lorentz angle ! • The CERN CLIC Linear Collider Detector Group (LCD) R&D focuses on these main aspects of the CLIC vertex detector: • Ultra-Thin Hybrid Planar Pixel Detector R&D Cooperation with Sensor producers for the production of Ultra-Thin Pixel Sensors compatible with CLIC requirements Design of Next Generation ASIC for hybridization with the sensors (in collaboration with Medipix/Timepix Collaboration) • CLICpix 65 nm prototype • Small. Pix 130 nm • Simulation of Hybrid Pixel Sensors in CLIC conditions (TCAD, MC, Digitization) • • • R&D on mechanics and cooling of the detector • • Low material budget stave design Air cooling • R&D on power delivery and power pulsing • • DC/DC Conversion + LDO Low mass cabling and module integration
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Sensor Simulation and Digitization In CLIC, thin sensor (~50 um) deplete a very low voltage (1 -10 V) leading to larger Lorentz angle in the drift of carriers We developped a set of simulation to study these effects in pixel sensors • Geant 4 simulation and Digitization model (Fast, needs to be calibrated to readout chip and sensors ) • TCAD simulation of thin pixel sensors. Slow approach but allow to solve the full system of equation, useful for tuning of simpler models • Monte-Carlo Charge Transport coupled to DC TCAD simulation. Allow for larget statistics, can be coupled to GEANT 4 We conducted a TB campain at CERN’s SPS with 180 Ge. V/c pions, using a Timepix ASIC coupled to a planar sensor to gather data to help us tune the digitization model in conjunction with our simulation 13
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan Sensor Simulation and Digitization • Test. Beam data will be compared to GEANT 4 simulation (MC and Simple model based Digitizer) of the telescope setup • The Simple Digitizer can be used to predict occupancy in the vertex layout we are investigate 14
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLIC Mechanics Integration and cooling F. Duarte Ramos, CERN 15
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLIC Mechanics Integration and cooling Ongoing work on the design of the disk and barrel support to minimize material budget and allow air cooling to be efficient. • Low mass carbon fiber shell (180 um CFRP) • Spiraling petal design Vibration and deformation analysis are being performed to evaluate the efficiency of cooling and vibration present in the barrel and disk structures F. Duarte Ramos, CERN 16
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLIC: Power delivery and Power Pusling • Power Pulsing with the Timepix chip • Not design for pulsing, large capacitance coming from single bias line for all pixel row • Possible to nevertheless power-pulse the preamp of the chip through its bias DAC • CERN SPS testbeam campaign in June 2012 • Power pulsing of the Chip and operation in synchronisation with a Tracking telescope (LHCb/Timepix Telescope) • Results are promising, showing full detection efficiency within 600 us 17
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLIC: Power delivery and Power Pusling 18
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 19 Small. Pix: general features Technology: 130 nm CMOS • • Goal: decrease pixel size compared to previous Medipix/Time. Pix chips (55 x 55 um 2 pixel) Features: • 130 nm Technology • ≈19 x 20 mm 2 chip size, 250 kpixel • Two ≈14 bit counters allow simultaneous Integral Time. Over-Threshold (TOT) • and Time Of Arrival (TOA) or simultaneous TOT and Photon Counting; Increase resolution (counters’ depths) using 2 x 2 Super. Pixels • Zero suppression in the pixel to compress data and speed up the readout • Zero suppression per column • Fast OR (provides a trigger) and fast Reset • Re-use High Density library from Medi. Pix 3 • Compatible with existing Readouts. • Power Pulsing Logic on Chip R. Ballabriga, M. De Gaspari, CERN Smallpix 32. 5µm 40µm Medipix 2/3, Timepix 1/3 55µm
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 20 Small. Pix: analog specifications, area & power estimate • • • Analog Design • Analog front-end in synergy with Time. Pix 3 development • Based on a Krummenacher feedback preamplifier and a singlethreshold discriminator • Small feedback capacitor => high gain => the system works in saturation for charges bigger than 12 ke • Analog noise ≈80 e-@Cdet=25 f. F, allowing thresholds as low as 500 e • Leakage current compensation: -10 n. A (e-), +20 n. A (h+) • Peaking time <25 -50 ns Digital Design • Timewalk <25 ns for Qin=1500 e • TOT monotonicity for big positive charges up to >300 kh+ • TOA resolution 1. 5 ns Footprint • Analog area: 630 -780 um 2 with 3 -4 bit pixel equalization DAC • Digital area: 575 um 2 for 10 bit, 644 um 2 for 12 bit, 705 um 2 for 14 bit • Equivalent to a Pixel size ≈40 x 40 um 2 with 14 bit TOT/TOA counters Power Consumption • Analog consumption: 7. 4 u. A/pixel (3 u. A single-ended preamplifier, 4 u. A discriminator); • Assuming 0. 5 u. A/pixel digital@1. 5 V => 740 m. W/cm 2, before power pulsing Submission target: Q 1/Q 2 2013. R Ballabriga, M De Gaspari, CERN 780 um 2 draft for Time. Pix 3
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan CLICPix: General Features • CLICPix is a pixel detector ASIC under development at CERN, implemented in 65 nm CMOS, driven by the requirements of CLIC vertex detectors • The main feature is the small pixel pitch (25 μm), which requires the use of a downscaled technology • Each pixel includes simultaneous 4 -bit TOA and TOT measurements • Photon Counting Mode is also available for threshold equalization purposes • Front-end timing accuracy aims to be less than 10 ns (timewalk can be corrected using the TOT measurement) • A (selectable) compression logic allows skipping pixels which were not hit during the acquisition. A clusterbased and column-based compression is also being implemented. This allows us to readout a full chip in less than 800 μs (for a 10% occupancy) using a 320 MHz readout clock P Valerio, CERN 21
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 22 CLICPix : Power consumption • The main contribution to the power consumption is the analog front-end, which would use ~2 W/cm 2 if run continuously • The submission for November 2012 with a Multi-Project Wafer (MPW) • A power pulsing scheme has been • The demonstrator will have a fully functional 64 by 64 pixel matrix Power implemented allowing for the reduction of the average power consumption to be less than 50 m. W/cm 2 (allowing the use of air cooling) 20 μs ~15 μs Bunch crossings (156 ns=0. 5 nsx 312) P Valerio, CERN t
Vertex Detectors for the future linear colliders, M. Benoit, Pixel 2012, September 2 -7 2012, Inawashiro, Japan 23 Conclusion • Future linear collider vertex detector present a new kind of challenge with regard to LHC • Less radiation damage but … • Higher precision (timing ~10 ns, SPR ~5 um) • Less power (2 u. W/channel, 50 m. W/cm 2) • Lower Material budget (50 -100 um of silicon, minimalist support structures) • R&D Converge toward a set of solution fullfilling the requirement for CLIC and ILC • CLIC Conceptual Design Report Volume 2 and Volume 3 are published • ILC Detector Baseline Document (DBD) in preparation, to be released end of 2012 Thanks for your attention ! ありがとう。
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