Vertex 2002 KailuaKona November 2002 Readout Concept for

Vertex 2002 Kailua-Kona, November 2002 Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing Marcel Trimpl Bonn University / MPI Munich (HLL) Kailua-Kona, 05. 11. 2002 L. Andricek, G. Lutz, P. Lechner, R. H. Richter, L. Strüder P. Fischer, I. Peric, M. Trimpl, J. Ulrici, N. Wermes Marcel Trimpl, Bonn University

DEPFET-Performance single-pixel spectra: • excellent energy resolution (low noise needed for thinned detector) Matrix-picture with 55 Fe: • thinnable (50µm proposed for TESLA) • small pixelsize possible (25 x 25µm 2) • good spatial resolution (charge sharing) • low power consumption (< 1 W for whole TESLA vtx-sensor) (row-wise operation) 55 Fe-spectra @ 300 K ENC = 4. 8 +/- 0. 1 Kailua-Kona, 05. 11. 2002 e- Þ fast and low noise readout needed !! [J. Ulrici, Bonn] ~ 3. 2 mm spatial resolution: ~ 9µm (with 50 x 50 µm 2 pixel) Marcel Trimpl, Bonn University

Proposed concept for TESLA matrix is read out row-wise • thin detector-area first thinned samples: down to 50µm • frame for mechanical stability carries readoutand steering-chips [L. Andricek, MPI Munich] Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Matrixoperation Matrix-scheme: Readout-scheme: • Advantages Select one row via external Gates and measure of readout: But: Pedestal + Signal current • Reset one row and measure pedestal currents complete reset (clear) needed • pedestals need not to gate be stored • Collected charge in internal ~ (Difference of both currents) • 1/f noise is reduced • continue with next row. . . (CDS) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Readout Architecture V 1. 0 DEPFET provides current + fast readout needed Þ current readout · Regulated Cascode keeps drain potential constant · (Signal+Pedestal) are stored in fast current memory cell (20 ns, inverting) · Pedestal-Current after Reset is subtracted automatically · Hit-Identification with fast current comparator · Hit-Information + analog value are stored in mixed-signal FIFO · FIFO is emptied row by row Fast digital scanner identifies hits in a row (up to 2 hits per cycle) and multiplexes the corresponding analog currents to the outputs (no external trigger) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

. . . and. . . it is easy to add new features • larger buffer to store several rows at front end possible (if reset is not fast enough) • analog signals: row-wise common-mode-rejection reduces common noise pickup remarkably • digital signals: neighbour logic (mark neighbour pixel of hit for readout even if they are below threshold) • more hit scanners can easily be added (if occupancy is higher than at TESLA) • on chip (algorithmic) ADC at the end (only needs to digitize hits – saves power) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Basic Storage Principle IDEPFET Storage phase: input- and sample-switch are closed. (storage capacitance is „parasitic“ gate-capacitance of nmos) Sampling phase: sample and input switch are opened ( voltage at capacitance „unchanged“ → current unchanged ) I = IDEPFET + IBias Kailua-Kona, 05. 11. 2002 Transfer phase: Output switch is closed. IDEPFET is flowing out. (done immediately after sampling) Marcel Trimpl, Bonn University

1. 5 mm Prototype-Chip 4 mm • TSMC 0. 25 µm process with radiation-tolerant layout • contains all basic parts of proposed design (various memory-cells, fast hit-finder, current comparator structures) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

high speed and high accurancy. . . 1. Bandwidth (speed – intrinsically high because of small capacitance) 2. Output conductance (negligible with cascode techniques) 3. charge injection (offset and signal depending) 4. Noise (sampling noise dominant) 5. Radiation tolerant design limits transistor parameters (geometry has to be angular) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

reduce charge injection Use of 2 stages: coarse and fine sampling Error of coarse stage is resampled by fine stage Þ Signal depending charge injection reduced If two successive sample-stages are used (like in readout-architecture) the offset is eliminated as well: Iout 1 = - Iin + dd. I Iout 2 = - Iin + dd. I = Iin + dd. I – dd. I = Iin Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

U 2 I I 2 U U 2 I Memory Cell input Testsetup for Memory Cells steering I 2 U ADC Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

measured linearity 0. 1% accurancy reached @ 25 MHz !! 2 memory cells with regulated cascode input (like in readout architecture) dynamic range depends on bias-current of memory cell (range vs. power) (10µA for DEPFET-readout needed) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Bandwith (speed) Simple model: High speed : small Cgate, large gm Realistic model: Still : small Cgate large gm careful for design highneeded speed to avoid oscillation. . . Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Noise from current sampling voltage sample-stage: (independent of RSwitch) current sample-stage: Low noise: Large C, small gm (contrary to high speed requirement) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

sampling noise Noise [ n. A] gm and CGate are not independent: • linked via geometry • speed requirement gives ratio (line indicating 50 MHz) present design (23. . . 29 n. A) ~ 30 electrons sampling noise ( assuming g. Q = 1 n. A /e- ) more than other noise contributions (e. g. pmos current source) Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

measured noise • low noise expected (< 30 electrons) • difficult to measure with simple testsetup → cascade of sampling stages on chip corresponds to calculation !! Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Summary of performance digital part: fast hit-finder and current-comparator-block work with desired speed (50 MHz) analog part (memory cell): speed: 25 MHz accurancy : 0. 1 % noise : < 30 electrons very encouraging result Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

next step. . TESLA prototype-system: • full 128 channel readout-chip working with DEPFET-Matrix at 50 MHz • Internal ADC optional Timing at TESLA : • » 1 ms Trainbunch • » 200 ms Trainpause Hits are stored in RAM during train and read out in pause Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University

Summary / Outlook • Concept with fast readout for HEP-Experiment (e. g. TESLA) with current mode signal processing presented • Architecture of current mode operating prototype-chip has a lot of advantages (low power, high linearity, high speed, wide dynamic range) and is versatile • First prototype shows encouraging results with nearly TESLA requirements: Speed has to be improved by better choice of cell parameters : 50 MHz possible • TESLA Prototype-System working with DEPFET-Matrix expected within 2003 Kailua-Kona, 05. 11. 2002 Marcel Trimpl, Bonn University