Verilog module counter input clock input reset output

Код на языке Verilog – простой счетчик module counter ( input clock, input reset,

Что делает схема 3 © 2012 MIPS Technologies, Inc. All rights reserved.

Схема после синтеза 4 © 2012 MIPS Technologies, Inc. All rights reserved.

Схема после синтеза - крупнее 5 © 2012 MIPS Technologies, Inc. All rights reserved.

Waveform - симуляция 6 © 2012 MIPS Technologies, Inc. All rights reserved.

Спасибо! At the core of the user experience® MIPS, MIPS 32, MIPS 64, MIPS-Based,

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Код на языке Verilog – простой счетчик module counter ( input clock, input reset, output logic [1: 0] n ); always @(posedge clock) begin if (reset) n <= 0; else n <= n + 1; endmodule 2 © 2012 MIPS Technologies, Inc. All rights reserved.

Спасибо! At the core of the user experience® MIPS, MIPS 32, MIPS 64, MIPS-Based, MIPS-Verified, MIPS Technologies logo are trademarks of MIPS Technologies, Inc. and registered in the U. S. Patent and Trademark Office. MIPS, MIPS 32, MIPS 64, MIPS-Based, MIPS Logo, MIPS Technologies Logo, Aptiv, micro. Aptiv, inter. Aptiv, pro. Aptiv, Cor. Extend, Pro Series, micro. MIPS, M 14 K, M 4 K, 4 KEc, 24 KE, 34 K, 74 K, 1004 K, 1074 K, MIPS Navigator, and FS 2 are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries. 7 © 2012 MIPS Technologies, Inc. All rights reserved.