Using Vivado HLS to Implement 8 K 4

Using Vivado HLS to Implement 8 K 4 K Scaler © Copyright 2013 Xilinx.

Introduction HLS can help to implement the complicated video processing easily, it is productive design tools to support the similar applications. The purpose of this design is to using HLS to design a 8 K 4 K scaler. With this demonstration, you can see that we can use HLS to build an algorithm quickly and verified it on HW easily, saving much of our efforts. HLS is very powerful and flexibility. . © Copyright 2013 Xilinx.

Technology Roadmap In the digital display market, the next innovation wave – SHV(Super Hi-Vision) 8 K 4 K is now emerging. w/o Glasses 3 D (100 view points) 60 Hz (Prototype）Natural 3 D without fatigue w/o Glasses 3 D (50 view points) 60 Hz 100 (Prototype) Smooth Motion Parallax 8 Kx 4 K 60 Hz 10 4 Kx 2 K 120 Hz 3 D(R/L) 240 Hz FHD 60 Hz 2008 3 D(Xpol) 60 Hz 2009 2010 Super High Vision 21 G Band Satellite Test Transmission Super High Vision Public Viewing 4 K 2 K 3 D(R/L) 120 Hz 4 Kx 2 K 60 Hz w/o Glasses 3 D (9 view points) 60 Hz 2011 2012 2013 2014 2015 2016 2017 Source: NEDO Strategic Technology Road Map 2009, NHK R&D Open House 2010, Comp. by Xilinx KK. © Copyright 2013 Xilinx. 2018 2019 2020 2021 2022

1080 p to 8 K 4 K Up-Converter 1 X 1080 p input scales to populate a 8 K 4 K display 1080 p Source HDMI Xilinx 7 Series V-by-OneⓇHS Up-converters are mandatory in 8 K 4 K displays Page 4 . © Copyright 2013 Xilinx.

Xilinx Scaler IP Status One key technology in either SHV or UHD is the Scaler. Unfortunately, currently Xilinx’s Scaler IP can only support 4 K 2 K processing, and there hasn’t a suitable solution to support 8 K 4 K . © Copyright 2013 Xilinx.

HLS is an efficient tool to implement various Image & Video Processing Algorithms C, C++ or System. C Image Processing • Defective Pixel Correction • Color Filter Array Interp • Color Correction Matrix • Gamma Correction • Color Space Conversion • Statistics Module • App example for AWB • Noise Reduction • Edge Enhancement VHDL or Verilog Video Processing • Video Scaler • On-Screen-Display • Motion Adaptive Noise Reduction • Image Characterization Compression • H. 264/MPEG-4 • MPEG-2 • MPEG-4 • JPEG-2000 • Scalable Video Coding • Multi-View Coding • Dolby • MJPEG Memory and timing • Timing Controller • AXI Interconnect • AXI Video DMA Key Image/Video processing IPs. © Copyright 2013 Xilinx. Connectivity • 10 G/1 G Ethernet • SDI • Ethernet AVB • Display port • HDMI/DVI • Camera Link

Conceptual Design Output Image Input Image Scaler Vivado HLS Design Specification Page 7 FPGA Kintex 7 / 7 Z 045 Clock Frequency > 150 MHz Input Data Rate 1 pixel per clock cycle Input Image Size 1920 x 1080 @ 60 frames per second Output Image Size 8 K x 4 K @ 60 frames per second . © Copyright 2013 Xilinx.

Scaler Algorithm Introduction Lanczos resampling Algorithm. – Video Scaling is a form of 2 D filter operation which can be approximated with the equation shown bellow – Usually this equation was separated into two 1 -D filter stages in sequence: a vertical filter stage and a horizontal filter stage: V-filter: H-filter: Page 8 . © Copyright 2013 Xilinx.

In this Application In this Design. – Vtaps = Htaps = 4 – Coefs: – TDP: ZC 706 – Target Frequency: 250 Mhz Page 9 . © Copyright 2013 Xilinx.

C Model C Raw Model: for (row_o=0, row_o<7680, row_o++) { for (col_o=0, col_o<4320, col_o++) { row_i = row_o/4; col_i = col_o/4; for (m=0, m<4, m++) { for (n=0, n<4, n++) { frame_o(row_o, col_o) + = frame_i(row_i+2 -m, col_i+2 -n) * coef(m, n); } } C Model can be used for simulation, but may not be suitable for HW Implementation for this case. – It just suitable to run on CPU-Cache-Memory architecture. © Copyright 2013 Xilinx.

Expected Scaler HW Structure using HLS Description. – read_buffer(): output = input, reserved for future use for algorithm upgrading. – frame_tmp 1 & frame_tmp 2 FIFO: used for data buffer . © Copyright 2013 Xilinx.

Vivado HLS Project Page 12 . © Copyright 2013 Xilinx.

C Code: Top level function An entire image is passed into the function as an array – Clean, intuitive code – Designer works at the image level . © Copyright 2013 Xilinx.

v_scaler Implementation v_sclaer() using 4 line-buffer – 1920 x 24 bit / line buffer . © Copyright 2013 Xilinx.

Top level function rtl ports The Interface of RTL Top can be easily configured in HLS . © Copyright 2013 Xilinx.

Resource VS Xilinx Scaler IP Resource Utilization of HLS (Based on 7 Z 045) Resource Utilization of Xilinx Scaler IP (K 7) Resource Utilization of HLS is very Impressive! ※ Page 16 . © Copyright 2013 Xilinx.

Timing Summary – XC 7045 -1 FFG 900 C – create_clock -period 4. 0 -name sys. Clk [get_ports ap_clk] – After Implementation in Vivado 2013. 02 Xilinx IP Clock Speed after Implemented: >250 Mhz. Amazing! Page 17 . © Copyright 2013 Xilinx.

Modelsim RTL simulation Simulation Environment – Using 1920 x 1080. bmp as imput. – Write result to 7680 x 4320. bmp – One frame simulation is enough. . © Copyright 2013 Xilinx.

Test Image: test_1920 x 1080. bmp Page 19 . © Copyright 2013 Xilinx.

RTL Simulation Result: result_7680 x 4320. bmp Page 20 . © Copyright 2013 Xilinx.

Simulation Results and Waveform Snapshoot Simulation Results – Input 1080 P 60, 16. 7 ms / fs. – Output 8 K 4 KP, 133 ms / fs, that is 8 fs/s. . © Copyright 2013 Xilinx.

HW Implementation – the number of scalers used can be reduced to only 8 (each running @ 250 Mhz). . © Copyright 2013 Xilinx.

Closed & Discussion HLS is very suitable for many Video & Imaging processing algorithms. There are many other algorithms like: – Noise Reduction – Image Rotate, Distortion – Edge Enhancement – Image Compression like JPEG, JPEG-LS …… 8 K 4 K Scaler should not be an end, but a beginning. © Copyright 2013 Xilinx.

Reference ug 871 -vivado-high-level-synthesis-tutorial xapp 890 -zynq-sobel-vivado-hls xapp 793 -memory-structures-video-vivado-hls . © Copyright 2013 Xilinx.

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