Use of Partial Orders for Analysis and Synthesis

Use of Partial Orders for Analysis and Synthesis of Asynchronous Circuits Alex Yakovlev School of EECE University of Newcastle upon Tyne Collaboration with A. Semenov, W. Vogler, A. Kondratyev, V. Khomenko, M. Koutny, A. Madalinski, I. Poliakov UFO’ 07 26 June 2007 Siedlce 1

Outline l l l l l Motivation A bit of history Circuit models in Petri nets Properties to be checked Problems with unfolding models State Coding analysis Visualisation using unfoldings Deriving logic from unfoldings What next? UFO’ 07 26 June 2007 Siedlce 2

Motivation for asynchronous systems l l l Asynchronous (self-timed) systems help variability-tolerant design and optimize powerperformance tradeoff for nanometer technology Latest International Semiconductor Roadmap predicts 20% (40%) of designs will be asynchronous, and by 2012 (2020) Active areas of asynchronous signalling and circuits: low power and low EMI processing (automotive, smart-card), networks on chip, GALS UFO’ 07 26 June 2007 Siedlce 3

Motivation from circuit analysis Self-timed circuits can be highly concurrent, e. g. use of pipeline data flow structures, use of parallel branches in control of CPUs, concurrent resource allocation schemes (multi -way arbiters, switches etc. ) – state space can run into 1030 for 100 s of signals. Hence analysis and verification using explicit state space traversal is hard l UFO’ 07 26 June 2007 Siedlce 4

Motivation from circuit synthesis l l In the synthesis domain, resolving state encoding problems and constructing nextstate functions using state space models is limited to 30 -40 signals (relatively small controllers) Visualisation of state space is very hard, let alone examining groups of states about some properties UFO’ 07 26 June 2007 Siedlce 5

Circuit specification UFO’ 07 26 June 2007 Siedlce 6

State Graph UFO’ 07 26 June 2007 Siedlce 7

Modified Specification UFO’ 07 26 June 2007 Siedlce 8

The new State Graph… UFO’ 07 26 June 2007 Siedlce 9

But how about this one? UFO’ 07 26 June 2007 Siedlce 10

A bit of history Early examples: l Flow chart, change chart methods by Gilles, Swartwout and Shelly – late 50 s, early 60 s l Signal Graphs for handshake control structures by Jump and Thiagarajan – mid 70 s l Circuit synthesis from Taxograms by Starodoubtsev – mid 80 s l Circuit analysis and synthesis using Change Diagrams and their unfoldings by Kishinevsky, Kondtayev, Taubin and Varshavsky – late 80 s. l Relation-based approach to analysis of STG models by Rosenblum and Yakovlev – late 80 s UFO’ 07 26 June 2007 Siedlce 11

A bit of history l l l l l Petri net unfolding prefix by Mc. Millan (1992) Unfolding prefix for STGs and circuits by Kondratyev et al. and Semenov (1995) Unfolding-based analysis of Timed Circuits by Semenov and Yakovlev (1996) Unfolding-based synthesis using cover approximations by Semenov et al. (1997) Circuit analysis using contextual net unfoldings by Vogler et al. – (1998) STG analysis using unfoldings and LP and SAT by Khomenko et al. (2002 -2003) Circuit Synthesis from STG using unfoldings and SAT by Khomenko (2004) Visualization of STG-based Synthesis by unfoldings by Madalinski et al. (2003 -2005) Combining decomposition and unfolding for STG-based Synthesis by Khomenko and Shaefer (2007) UFO’ 07 26 June 2007 Siedlce 12

Circuit models in Petri nets l l Event-based models: Petri net transitions represent signal events Level-based models: Petri net places model the values of signals UFO’ 07 26 June 2007 Siedlce 13

Logic Circuit Modelling Event-driven elements Petri net equivalents C Muller Celement Toggle UFO’ 07 26 June 2007 Siedlce 14

Logic Circuit Modelling Petri net equivalents Level-driven elements y(=0) x(=1) x=0 y=1 y=0 x=1 NOT gate Read arcs x=0 x(=1) z(=0) z=1 y=0 y(=1) NAND gate z=0 b x=1 y=1 UFO’ 07 26 June 2007 Siedlce 15

Circuit Petri Nets Petri net equivalents Level-driven elements y(=0) x(=1) Self-loops in ordinary P/T nets x=0 y=1 y=0 x=1 NOT gate x=0 x(=1) z(=0) z=1 y=0 y(=1) NAND gate z=0 b x=1 y=1 UFO’ 07 26 June 2007 Siedlce 16

Logic Circuit Modelling: examples Data In Pipeline data Stage Data Out • Handshake protocols between the stages Data Enable Rin Ain Rout Pipeline control Stage UFO’ 07 26 June 2007 Siedlce Pipeline control must guarantee: Aout • Safe propagation of the previous datum before the next one 17

Event-driven circuit Non-speedindependence can be detected via non-1 -safeness check UFO’ 07 26 June 2007 Siedlce 18

Level-driven circuit UFO’ 07 26 June 2007 Siedlce 19

Level-driven circuit Set-part UFO’ 07 26 June 2007 Siedlce 20

Level-driven circuit Reset-part UFO’ 07 26 June 2007 Siedlce 21

Level-driven circuit Without y 2 in Set part of y 1 this trace can happen: I 2+ C 1+ I 2 - C 2+ I 1+ C 1 C 2 - I 2+ C 1+ UFO’ 07 26 June 2007 Siedlce This sort of structures (acyclic Change Diagrams) were built directly from logic eqn’s by Kishinevsky et al. – but only for distributive circuits 22

Level-driven circuit Without y 2 in Set part of y 1 this trace can happen: I 2+ C 1+ I 2 - C 2+ I 1+ C 1 C 2 - I 2+ C 1+ disabling UFO’ 07 26 June 2007 Siedlce 23

Properties analysed l l Functional correctness (need to model environment) Deadlocks Hazards: – non-1 -safeness for event-based – non-persistency for level-based Timing constraints – Absolute (need Timed Petri nets) – Relative (compose with a PN model of order conditions) UFO’ 07 26 June 2007 Siedlce 24

Circuit Petri Nets Petri net equivalents Level-driven elements y(=0) x(=1) Self-loops in ordinary P/T nets x=0 y=1 y=0 x=1 NOT gate x=0 x(=1) z(=0) z=1 y=0 y(=1) NAND gate z=0 b x=1 y=1 UFO’ 07 26 June 2007 Siedlce 25

Unfolding Nets with Read Arcs PN with selfloops Unfolding with self-loops Combinatorial explosion due to splitting the self-loops UFO’ 07 26 June 2007 Siedlce Unfolding with read arcs (work with W. Vogler, CONCUR 1998) Works nicely for readpersistent nets only 26

Petri Net mapping: an example corresponding Petri Net source gate-level model Multiple read arcs Only one readone arcplace: per place: exiting minimal on unfolding badimpact for unfolding! UFO’ 07 26 June 2007 Siedlce 27

Unfolding and read arcs: statistics Without place splitting With place splitting Net size (places/ transitions) N of events Unfolding time Counterflow stage controller 24/28 1541 36 ms 821 25 ms SDFS ARISC 90/90 >50000 >1 min (halted) 164 18 ms SDFS fork/join 112/132 >50000 >1 min (halted) 1055 134 ms SDFS fork/join early prop. 112/134 >50000 >1 min (halted) 1790 277 ms Test case UFO’ 07 26 June 2007 Siedlce 28

STG Unfolding l l Unfolding an interpreted Petri net, such as a Signal Transition Graph, requires keeping track of the interpretation – each transition is a change of state of a signal, hence each marking is associated with a binary state The prefix of an STG must not only “cover” the STG in the Petri net (reachable markings) sense but must also be complete for analysing the implementability of the STG, namely: consistency, output-persistency and Complete State Coding UFO’ 07 26 June 2007 Siedlce 29

STG Unfolding STG Uninterpreted PN Reachability Graph p 1 a+ p 2 p 1 b+ p 2 p 3 c+ c+ p 4 d+ p 5 STG unfold. prefix p 1 abcd p 1(0000) p 3 p 4 Binary-coded STG Reach. Graph (State Graph) a+ b+ p 3(0100) p 2(1000) c+ c+ p 4(1010) p 4(0110) d+ d+ a+ p 2 b+ p 3 c+ c+ d+ d+ p 5 d. UFO’ 07 26 June 2007 Siedlce p 4 p 5(1011) p 5(0111) p 5 d- d 30

STG Unfolding STG Uninterpreted PN Reachability Graph p 1 a+ p 2 p 1 b+ p 2 p 3 c+ c+ p 4 p 5 STG unfold. prefix p 1 abcd p 1(0000) p 3 p 4 Binary-coded STG Reach. Graph (State Graph) a+ b+ p 3(0100) p 2(1000) c+ c+ p 4(1010) p 4(0110) d+ d+ a+ p 2 p 3 c+ c+ p 4 p 5(1011) p 5(0111) d+ b+ d+ p 5 d. UFO’ 07 26 June 2007 Siedlce Not like that! p 5 d 31

Consistency and Signal Deadlock STG a+ PN Reach. Graph p 1 p 6 b+ ba+ p 3 p 6 p 2 p 6 b+ p 2 p 3 a- p 6 b+ b- bp 2 p 6(10) p 3 p 6(01) a- p 1 p 4 b+ p 2 p 4 p 3 p 4 b+ b- p 2 p 5 b+ b+ UFO’ 07 26 June 2007 Siedlce bp 1 p 4(00) b+ a+ b+ b- p 1 p 5 b+ bp 3 p 5 b- p 5 ab p 1 p 6(00) b+ a+ aa+ b- p 4 STG State Graph p 2 p 4(10) p 3 p 4(01) p 1 p 5(01) b+ b- p 2 p 5(11) Signal deadlock wrt b+ (coding consistency violation) 32

Signal Deadlock and Autoconcurrency STG a+ STG State Graph p 1 bp 1 p 4(00) b+ a+ b+ p 6 b+ bp 5 b+ a+ p 3 p 2 a- b- p 4 ab bp 2 p 6(10) p 3 p 6(01) p 3 a- p 1 STG Prefix p 1 p 6(00) b+ a+ b+ p 2 p 6 p 2 p 4(10) p 3 p 4(01) p 1 p 5(01) a- UFO’ 07 26 June 2007 Siedlce p 1 p 4 b+ b+ p 2 p 5(11) Signal deadlock bwrt b+ (coding consistency violation) b- b+ p 2 a+ p 5 p 2 b- b- Autoconcurrency wrt b+ 33

Verifying STG implementability l l l Consistency – by detecting signal deadlock via autoconcurrency between transitions labelled with the same signal (a* || a*, where a* is a+ or a-) Output persistency – by detecting conflict relation between output signal transition a* and another signal transition b* Complete State Coding is less trivial – requires special theory of binary covers on unfolding segments UFO’ 07 26 June 2007 Siedlce 34

Example: VME Bus Controller Data Transceiver d dsr dtack VME Bus Controller dtackd- ldsdsr- UFO’ 07 26 June 2007 Siedlce lds ldtack dsr+ lds+ ldtack+ Device Bus ldtack+ d+ 35

Example: Encoding Conflict 00100 ldtack 01100 lds 01110 dtackldtack- lds+ ldtack- dtack 01000 dsr+ 10010 11000 ldsldsdtackdsr+ 01010 11010 M’’ ldtack+ M’ 11010 d+ d- dsr 01111 UFO’ 07 26 June 2007 Siedlce 10000 dsr+ 00000 dtack+ 11111 11011 36

Example: Encoding Conflict e 8 e 1 e 2 e 3 e 4 dsr+ lds+ ldtack+ d+ Code(conf’)=10110 UFO’ 07 26 June 2007 Siedlce e 5 e 6 dtack+ dsr- Code(conf’’)=10110 e 7 e 10 dtack- dsr+ e 12 lds+ dlds- ldtack- e 9 e 11 37

Detection of encoding conflicts using SAT solvers l. A special case of model checking! l has the form CONF 1 CONF 2 VIOL l VIOL is a constraint stating that the two configurations have the same final encodings and enable different sets of output signals UFO’ 07 26 June 2007 Siedlce 38

Beyond model checking Problem: model checking just tells you whether some property holds, but it’s not enough for resolution of encoding conflicts and for deriving equations! UFO’ 07 26 June 2007 Siedlce 39

Example: Resolving the conflict 001000 dtack- ldtack 011000 lds 011100 d- ldtack- dsr+ 000000 lds+ dsr+ 100101 110000 ldtack+ ldsldsdtackdsr+ 110100 M’’ M’ 11010100 d+ csc- 011110 UFO’ 07 26 June 2007 Siedlce 100001 ldtack- dtack 010000 csc+ 100000 011111 dsr- dtack+ 111111 110111 40

Example: Encoding Conflict e 8 core e 1 e 2 e 3 e 4 dsr+ lds+ ldtack+ d+ Code(conf’)=10110 UFO’ 07 26 June 2007 Siedlce e 5 e 6 dtack+ dsr- Code(conf’’)=10110 e 7 e 10 dtack- dsr+ e 12 lds+ dlds- ldtack- e 9 e 11 41

Example: Resolving the conflict dtack- dsr+ csc+ lds+ d- lds- ldtack+ csc- dsr- dtack+ d+ UFO’ 07 26 June 2007 Siedlce 42

Visualising conflicts: Height map l l l Cores often overlap Highest ‘peaks’ are good candidates for signal insertion Analogy with topographic maps Core 1 Core 2 A 1 A 2 A 3 Core 3 UFO’ 07 26 June 2007 Siedlce 43

Height map: an example Highest peak csc+ Core map UFO’ 07 26 June 2007 Siedlce Height map 44

Logic synthesis: Next-state function l l l The next-state function of each output or internal signal will be implemented as a logic gate in the circuit Defined for each such signal z at each reachable state M as Nxtz(M) = Codez(M) Enabledz(M) The value is undefined (‘don’t care’) for unreachable states UFO’ 07 26 June 2007 Siedlce 45

Example: Deriving equations 001000 dtack- ldtack 011000 lds 011100 ldtack- dsr+ 000000 100001 lds+ ldtack- dtack 010000 csc+ 100000 dsr+ 100101 110000 ldtack+ ldsldsdtackdsr+ 110100 010100 110101 d+ dcsc 011110 UFO’ 07 26 June 2007 Siedlce 011111 dsr- dtack+ 111111 110111 46

Example: Deriving Equations Code 001000 000000 100001 011000 010000 100101 011100 010100 110101 011110 011111 110111 Nxtdtack 0 0 0 1 1 Nxtlds 0 0 0 1 1 1 Nxtd 0 0 0 1 1 1 Nxtcsc 0 0 1 1 0 0 0 1 1 Eqn d d csc ldtack dsr ( ldtack csc) UFO’ 07 26 June 2007 Siedlce 47

Example: Resulting Circuit Data Transceiver Bus d dtack dsr csc Device lds ldtack UFO’ 07 26 June 2007 Siedlce 48

Logic synthesis on unfoldings Challenge: how to do this without building the state graph, and using only the unfolding prefix? UFO’ 07 26 June 2007 Siedlce 49

Logic synthesis on unfoldings l l l Problem: given a prefix and a set X of signals which are known to be a support of the given output or internal signal z, compute the truth table of Nxtz Let = CONF CODEX where CODEX relates the values of all signals in X with the configuration Compute the projection of onto X Need to know how to compute projections! UFO’ 07 26 June 2007 Siedlce 50

Example: computing projections a 0 0 0 0 1 1 1 1 b 1 1 1 1 0 0 0 0 c 0 0 0 1 1 1 1 d 0 1 1 0 0 1 1 e 1 0 1 0 1 0 1 UFO’ 07 26 June 2007 Siedlce a b =(a b)(c d e) Proj{a, b, c} a 0 0 1 1 b 1 1 0 0 c 0 1 51

Computing projections a b =(a b)(c d e) (a b c)(a b c) Proj{a, b, c} a b c d e 0 1 0 1 1 0 0 UNSAT UFO’ 07 26 June 2007 Siedlce Incremental SAT 52

Further developments l l Unfoldings for PNs with read arcs, beyond read -persistent nets Unfoldings for large circuit models (higher levels) Unfoldings of circuits with timing constraints Unfoldings for synthesis and re-synthesis driven by verification and optimization UFO’ 07 26 June 2007 Siedlce 53

Circuit Petri nets The meaning of these numerous self-loop arcs is however different from self-loops (which take a token and put it back) These should be test or read arcs (without consuming a token) From the viewpoint of analysis we can disregard this semantic discrepancy (it does not affect reachability graph properties!) and use ordinary PN unfolding prefix for analysis, BUT … UFO’ 07 26 June 2007 Siedlce 54

Experimental results (from Semenov) Example with inconsistent STG: PUNT quickly detects a signal deadlock “on the fly” while Versify builds the state space and then detects inconsistent coding UFO’ 07 26 June state 2007 Siedlce 55

General-purpose Petri Net mapping technique read arcs • Signals are represented as elementary cycles • Positive (negative) transitions of the cycles are built according to set (reset) logical function • The logical functions are converted into DNF form and undergo boolean minimisation • For each clause of the minimised DNF, a transition is added • Transitions are connected to places corresponding to the literals of the DNF clause by means of read arcs UFO’ 07 26 June 2007 Siedlce 56