Universally Testable ANDEXOR Networks Ugur Kalay Marek Perkowski

Universally Testable AND-EXOR Networks Ugur Kalay, Marek Perkowski, Douglas Hall Speaker: Alan Mishchenko Portland State University

Agenda • Introduction – desired properties of a test set – testing AND and EXOR gates – test scheme proposed by Reddy • Testing Two-level AND-EXOR Networks – implementation of the new testing scheme – experimental results • Testing Multi-Level AND-EXOR Networks – extending the scheme for multi-level circuits • Conclusions and Directions of Future Research 2

Introduction Requirements for a Test Set • 100% Fault Coverage – no fault simulation • Minimal (as few tests as possible) – shorter testing time • Universal (does not depend on the circuit) – portability of the pattern generator – reduced engineering • Regular (test patterns have certain structure) – simpler pattern generator • Good Scalability – easy pattern generator expandability 3

Introduction Testing AND gate 1 a b c b 1 1 0 1 3 Faults Tests a 1 0 1 1 4 2 1 c 1 1 1 0 2 3 4 sa 0 sa 1 + + + + + 4

Introduction Testing EXOR gate a g b Inputs Class A a 0 0 1 1 b 0 1 Faults detected g 5, g 6, g 7, g 10 g 2, g 3, g 4 g 8, g 11 g 9 Class B a b g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g 10 g 11 g 12 g 13 g 14 g 15 g 16 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 5

Introduction • Reddy’s Positive Polarity Reed-Muller Testing Scheme Example: f = x 1 x 2 Å x 1 x 3 Å x 1 x 2 x 3 x 0 0 T 1= 0 1 1 x 1 0 1 x 2 0 1 x 3 0 1 x 0 T 2= - x 1 0 1 1 x 2 1 0 1 x 3 1 1 0 -: don’t care * 100% Single Stuck-at Fault Coverage * Minimal (C = n + 4) * Universal * Regular Patterns * Linear increase * Large expression leads to long EXOR cascade 6

Introduction • Other Reed-Muller Canonical Forms PPRM (Positive Polarity Reed-Muller) x 1 x 2 x 3 Å x 1 x 2 FPRM (Fixed Polarity Reed-Muller) x 1 x 2 x’ 3 Å x 2 x’ 3 GRM (Generalized Reed-Muller) x 1 Å x 2 Å x’ 2 x’ 3 • Free Expression ESOP GRM FPRM PPRM ESOP (EXOR-Sum-of-Products) x 1 x 2 x 3 Å x’ 1 x’ 2 x’ 3 7

Introduction • Comparison of the Number of Product Terms: 8

Testing Two-level AND-EXOR Networks * 100% single stuck at faults * Minimal C = n + 6 * Universal * Regular * Linear size increase * Perfect for BIST ! 9

Testing Two-level AND-EXOR Networks Advantages of deterministic testing for ESOP • much shorter test cycle than pseudo-random and pseudoexhaustive test sets • better fault coverage than a pseudo-random test set • no test point insertion required • a fixed, simple, and easily expandable pattern generator 10

Testing Two-level AND-EXOR Networks • Built-in Self-Test Circuitry for ESOP Networks PRPG EDPG ESOP Deterministic Pattern Generator Easily Testable 2 -level Circuit Under. ESOP Test Network MISR 11

Testing Two-level AND-EXOR Networks • ESOP Deterministic Pattern Generator • • Linearly expandable No initialization seed & circuitry Much shorter cycle than a PRPG Comparable size to PRPG (see later) 12

Testing Two-level AND-EXOR Networks • FSM (Part II) for EDPG 13

Testing Two-level AND-EXOR Networks Experimental Results • Comparisons of the number of test vectors for 100% single stuckat fault coverage 14

Testing Two-level AND-EXOR Networks • Comparisons of the number of test vectors for 100% single stuckat fault coverage (cont…) 15

Testing Two-level AND-EXOR Networks • Area and delay comparisons (LSI Logic Corp. , 0. 5 micron) 16

Testing Two-level AND-EXOR Networks • Area comparisons (Cont. . . ) 17

Testing Two-level AND-EXOR Networks • Multiple Fault Simulation Results 18

Testing Multi-level AND-EXOR Networks • Two-level implementations – easily testable – large delay • It is possible to factorize the two-level ESOP expression • Universal testing of two-level ESOPs can be adopted for multi-level testing – requires scan registers 19

Testing Multi-level AND-EXOR Networks Example: The multi-output function, X = acefg Å ace’f’g’ Å ad’efg Å ad’e’f’g’ Å ajh’i Å ajd Å b’cefg Å b’ce’f’g’ Å b’d’efg Å b’d’e’f’g’ Å b’h’ij Å bdj Y = bg’ Å a’cefg Å a’d’efg Z = adj Å b’dj Å ah’ij Å b’h’ij can be factorized as, X = U[V(efg Å e’f’g’) Å j. W] Y = bg’ Å a’efg. V Z = j. UW where, U = a Å b’ V = c Å d’ W = h’i Å d 20

Testing Multi-level AND-EXOR Networks • Implementation without testability improvements 21

Testing Multi-level AND-EXOR Networks • Inserting Literal Part 22

Testing Multi-level AND-EXOR Networks • Inserting Check Part 23

Testing Multi-level AND-EXOR Networks • Creating cascade of EXOR gates at each level 24

Testing Multi-level AND-EXOR Networks • Identifying ESOP Planes 25

Testing Multi-level AND-EXOR Networks • Inserting specialized Scan Registers and Scan Path 26

Testing Two-level AND-EXOR Networks TESTING SCHEME: • Each level is tested separately (can be improved) • ESOP planes of the same level are tested in parallel • Test vectors of the first level are applied from the primary inputs in parallel • Test vectors of the internal levels are applied from the primary inputs and from the scan registers • The bits applied from the scan registers are shifted into the scan path before applied in parallel • The network results are collected by the scan registers and shifted out, and/or observed from the primary outputs 27

Testing Multi-level AND-EXOR Networks • Implementation of Scan Registers • In normal circuit operation, only one mux delay added • Inserted only at the output of internal ESOP planes 28

Testing Multi-level AND-EXOR Networks • Scan Register mode of operations 29

Testing Multi-level AND-EXOR Networks • Scan Register mode of operations 30

Testing Multi-level AND-EXOR Networks • Scan Register mode of operations 31

Testing Multi-level AND-EXOR Networks • Critical Path Delay = 2. 95 ns vs. 4. 33 ns of 2 -level impl. 32

Testing Multi-level AND-EXOR Networks • (4 AND 3 + 5 AND 2 + 24 EXOR 2) gates + 5 SR vs. (17 AND 3 + 24 AND 2 + 33 EXOR 2) gates of 2 -level impl. 33

Future Directions • Developing a universal test set for bridging and stuckopen faults • Developing a factorization/decomposition method targeting EXOR-based multi-level synthesis and universal (deterministic) testability 34

Advantages and Disadvantages of the New Scheme • Test set is exponentially smaller than a pseudorandom test set and much smaller than algorithmically generated test set for 100% coverage of single stuck-at faults • Properties of deterministic pattern generator for BIST – easy to implement (small area overhead) – does not require seed generation – guarantees 100% testability • Detects significant fraction of multiple stuck-at faults and bridging faults • Cascade of EXOR gates is relatively slow • Area of the AND-EXOR circuit is relatively large • ESOP factorization algorithm is computationally complex 35

Rereferences [1] Ugur Kalay, Douglas V. Hall, Marek A. Perkowski. “A Minimal Universal Test Set for Self-Test of EXOR-Sum-of. Products Circuits”. IEEE Trans. Comp. Vol. 49, N 3, March 1999, pp. 267 -276. [2] Ugur Kalay, Marek Perkowski. “Rectangle Covering Factorization of EXORs into Scan-Based Levelized Circuits with Universal Test Set”. Proc. of International Workshop on Application of Reed-Muller Expansion in Circuit Design. 1999. 36