Unit 3 8086 Programming 8086 Registers RCET Microprocessor

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Unit 3 8086 Programming

Unit 3 8086 Programming

8086 Registers RCET Microprocessor & Microcontroller 3

8086 Registers RCET Microprocessor & Microcontroller 3

General Purpose Registers AX - the Accumulator BX - the Base Register CX -

General Purpose Registers AX - the Accumulator BX - the Base Register CX - the Count Register DX - the Data Register • Normally used for storing temporary results • Each of the registers is 16 bits wide (AX, BX, CX, DX) • Can be accessed as either 16 or 8 bits AX, AH, AL RCET Microprocessor & Microcontroller 4

 • AX General Purpose Registers – Accumulator Register – Preferred register to use

• AX General Purpose Registers – Accumulator Register – Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code – Must be used in multiplication and division operations – Must also be used in I/O operations • BX – Base Register – Also serves as an address register RCET Microprocessor & Microcontroller 5

General Purpose Registers • CX – Count register – Used as a loop counter

General Purpose Registers • CX – Count register – Used as a loop counter – Used in shift and rotate operations • DX – Data register – Used in multiplication and division – Also used in I/O operations RCET Microprocessor & Microcontroller 6

Pointer and Index Registers • All 16 bits wide, L/H bytes are not accessible

Pointer and Index Registers • All 16 bits wide, L/H bytes are not accessible • Used as memory pointers – Example: MOV AH, [SI] • Move the byte stored in memory location whose address is contained in register SI to register AH • IP is not under direct control of the programmer RCET Microprocessor & Microcontroller 7

Flag Register Overflow Carry Direction Parity Auxiliary Carry Interrupt enable Trap Zero Sign RCET

Flag Register Overflow Carry Direction Parity Auxiliary Carry Interrupt enable Trap Zero Sign RCET Microprocessor & Microcontroller 6 are status flags 3 are control flag 8

Memory segmentation and addressing • Von – Newman architecture & Harvard architecture • Program

Memory segmentation and addressing • Von – Newman architecture & Harvard architecture • Program Memory & Data Memory • Need for Segmentation – – – RCET To implement Harvard architecture Easy to debug Same Interfacing ICs can be used To avoid overlap of stack with normal memory Compatible with 8085 Microprocessor & Microcontroller 9

Segmented Memory RCET Microprocessor & Microcontroller 10

Segmented Memory RCET Microprocessor & Microcontroller 10

Memory Address Generation • The BIU has a dedicated adder for determining physical memory

Memory Address Generation • The BIU has a dedicated adder for determining physical memory addresses. Offset Value (16 bits) 0000 Segment Register (16 bits) Adder Physical Address (20 Bits) RCET Microprocessor & Microcontroller 11

Segment : Offset Address • Logical Address is specified as segment: offset • Physical

Segment : Offset Address • Logical Address is specified as segment: offset • Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address. • Thus the physical address of the logical address A 4 FB: 4872 is: A 4 FB 0 + 4872 A 9822 RCET Microprocessor & Microcontroller 12

Segments, Segment Registers & Offset Registers • Segment Size = 64 KB • Maximum

Segments, Segment Registers & Offset Registers • Segment Size = 64 KB • Maximum number of segments possible = 14 • Logical Address – 16 bits • Physical Address – 20 bits • 2 Logical Addresses for each Segments. – Base Address (16 bits) – Offset Address (16 bits) • Segment registers are used to store the Base address of the segment. RCET Microprocessor & Microcontroller 13

Segments, Segment Registers & Offset Registers • 4 Segments in 8086 – Code Segment

Segments, Segment Registers & Offset Registers • 4 Segments in 8086 – Code Segment (CS) – Data Segment (DS) – Stack Segment (SS) – Extra Segment (ES) RCET SEGMENT REGISTER OFFSET REGISTER Code Segment CSR Instruction Pointer (IP) Data Segment DSR Source Index (SI) Extra Segment ESR Destination Index (DI) Stack Segment SSR Stack Pointer (SP) / Base Pointer (BP) Microprocessor & Microcontroller 14

Memory Organisation

Memory Organisation

Memory Banking RCET Microprocessor & Microcontroller 16

Memory Banking RCET Microprocessor & Microcontroller 16

Accessing Data Memory q There are number of methods to generate the memory address

Accessing Data Memory q There are number of methods to generate the memory address when accessing data memory. These methods are referred to as Addressing Modes q Examples: — Direct addressing: MOV AL, [0300 H] 1 2 3 4 0 0 3 0 0 Memory address 1 2 6 4 0 DS (assume DS=1234 H) — Register indirect addressing: MOV AL, [SI] 1 2 3 4 0 0 3 1 0 Memory address 1 2 6 5 0 DS (assume DS=1234 H) (assume SI=0310 H) 3 -17

Addressing Modes • Operands in an instruction – Registers AX – Numbers immediate 12

Addressing Modes • Operands in an instruction – Registers AX – Numbers immediate 12 H – Memory • Direct addressing [3965] • Register indirect [BX] • Based relative addressing mode [BX+6], [BP]-10 • Indexed relative addressing mode [SI+5], [DI]-8 • Based indexed addressing mode

Operand types 1) Register - Encoded in instruction • Fastest executing • No bus

Operand types 1) Register - Encoded in instruction • Fastest executing • No bus access (in instr. queue) • Short instruction length 2) Immediate - Constant encoded in instruction • 8 or 16 bits • No bus access (in instr. queue) • Can only be source operand 3) Memory – in memory, requires bus transfer • Can require computation of address • Address of operand DATA is Called EFFECTIVE ADDRESS

Effective Address • Computed by EU • In General, Effective address = displacement +

Effective Address • Computed by EU • In General, Effective address = displacement + [base register]+ [index register] (if any) • Any Combination of These 3 Values – Leads to Several Different Addressing Modes • Displacement – 8 or 16 bit Constant in the Instruction – “base register” Must be BX or BP – “index register” Must be SI or DI

mov Direct Addressing [7000 h], ax ds: 7000 h mov ax es: [7000 h],

mov Direct Addressing [7000 h], ax ds: 7000 h mov ax es: [7000 h], ax es: 7000 h A 3 00 70 26 A 3 00 70 ax prefix byte - longer instruction - more fetch time opcode mod r/m displacement effective address

mov Register Indirect Addressing al, [bp] ; al gets 8 bits at SS: BP

mov Register Indirect Addressing al, [bp] ; al gets 8 bits at SS: BP mov ah, [bx] ; ah gets 8 bits at DS: BX mov ax, [di] ; ax gets 16 bits at DS: SI mov eax, [si] opcode ; eax gets 32 bits at DS: SI mod r/m BX BP SI DI effective address

Based Indirect Addressing mov al, [bp+2] ; al gets 8 bits at SS: BP+2

Based Indirect Addressing mov al, [bp+2] ; al gets 8 bits at SS: BP+2 mov ah, [bx-4] ; ah gets 8 bits at DS: BX-4 opcode mod r/m BX BP displacement + effective address

Indexed Indirect Addressing mov ax, DS: SI+1000 h [si+1000 h] ; ax gets 16

Indexed Indirect Addressing mov ax, DS: SI+1000 h [si+1000 h] ; ax gets 16 bits at mov eax, DS: SI+300 h [si+300 h] ; eax gets 32 bits at Mov [di+100 h], opcode al mod r/m DI SI ; DS: DI+100 h gets 8 bits in al displacement + effective address

Based Indexed Indirect Addressing mov ax, [bp+di] ; ax gets 16 bits at SS:

Based Indexed Indirect Addressing mov ax, [bp+di] ; ax gets 16 bits at SS: BP+DI mov ax, [di+bp] ; ax gets 16 bits at DS: BP+DI mov eax, [bx+si+10 h] ; eax gets 32 bits at DS: BX+SI+10 h mov cx, [bp+si-7] ; cx gets 16 bits at SS: BP+SI-7 opcode mod r/m displacement DI SI BX BP + + effective address

Addressing Mode Examples mov mov mov mov mov al, di, eax, al, cx, ebx,

Addressing Mode Examples mov mov mov mov mov al, di, eax, al, cx, ebx, al, ch, ds, al, ah, ax, eax, al, bx, al, ax, bl bp eax 12 faceh 2 h LIST DATA 2 [bp] [bx] [bp+2] [bx-4] LIST[bp] LIST[bx] LIST[bp+2] LIST[bx-12 h] ; 8 -bit register addressing ; 16 -bit register addressing ; 32 -bit register addressing ; 8 -bit immediate, al<-0 ch ; 16 -bit immediate, cx<-64, 206 ; 32 -bit immediate, ebx<-00000002 h ; al<-8 bits stored at label LIST ; ch<-8 bits stored at label DATA ; ds<-16 bits stored at label DATA 2 ; al<-8 bits stored at SS: BP ; ah<-8 bits stored at DS: BX ; ax<-16 bits stored at SS: BP ; eax<-32 bits stored at DS: BX ; al<-8 bits stored at SS: (BP+2) ; ax<-16 bits stored at DS: (BX-4) ; al<-8 bits stored at SS: (BP+LIST) ; bx<-16 bits stored at DS: (BX+LIST) ; al<-8 bits stored at SS: (BP+2+LIST) ; ax<-16 bits stored at DS: (BX 18+LIST) Register Immediate Direct Based

More Addressing Mode Examples mov mov mov mov mov al, ah, ax, eax, al,

More Addressing Mode Examples mov mov mov mov mov al, ah, ax, eax, al, bx, al, ah, ax, eax, al, ax, [si] ; al<-8 bits stored at DS: SI [di] ; ah<-8 bits stored at DS: DI [si] ; ax<-16 bits stored at DS: SI [di] ; eax<-32 bits stored at DS: DI Indexed es: [di] ; ax<-16 bits stored at ES: DI [si+2] ; al<-8 bits stored at DS: (SI+2) [di-4] ; ax<-16 bits stored at DS: (DI-4) LIST[si] ; al<-8 bits stored at DS: (SI+LIST) LIST[di] ; bx<-16 bits stored at DS: (DI+LIST) LIST[si+2] ; al<-8 bits stored at DS: (SI+2+LIST) LIST[di-12 h] ; ax<-16 bits stored at DS: (DI-18+LIST) [bp+di] ; al<-8 bits from SS: (BP+DI) ds: [bp+si] ; ah<-8 bits from DS: (BP+SI) Based [bx+si] ; ax<-16 bits from DS: (BX+SI) Indexed es: [bx+di] ; eax<-32 bits from ES: (BX+DI) LIST[bp+di] ; al<-8 bits from SS: (BP+DI+LIST) LIST[bx+si] ; ax<-16 bits from DS: (BX+SI+LIST) LIST[bp+di-10 h] ; al<-8 bits from SS: (BP+DI-16+LIST) LIST[bx+si+1 AFH] ; ax<-16 bits from DS: (BX+SI+431+LIST)

8086 Instruction Pipelining

8086 Instruction Pipelining

FETCH 1000: 0005

FETCH 1000: 0005

FETCH 10005

FETCH 10005

FETCH 10005 LOW HIGH

FETCH 10005 LOW HIGH

FETCH 10005 88 LOW HIGH

FETCH 10005 88 LOW HIGH

FETCH 10005 88 LOW HIGH

FETCH 10005 88 LOW HIGH

INC. PC

INC. PC

INC. PC

INC. PC

DECODE mov [bx], ?

DECODE mov [bx], ?

FETCH CS: IP

FETCH CS: IP

FETCH 1000: 0006

FETCH 1000: 0006

FETCH 10006

FETCH 10006

FETCH 10006 LOW HIGH

FETCH 10006 LOW HIGH

FETCH 10006 07 LOW HIGH

FETCH 10006 07 LOW HIGH

FETCH 10006 07 LOW HIGH

FETCH 10006 07 LOW HIGH

INC. PC

INC. PC

INC. PC

INC. PC

DECODE mov [bx], al

DECODE mov [bx], al

EXECUTE mov [bx], al DS: BX

EXECUTE mov [bx], al DS: BX

EXECUTE mov [bx], al 2000: 0023

EXECUTE mov [bx], al 2000: 0023

EXECUTE mov [bx], al 20023

EXECUTE mov [bx], al 20023

EXECUTE mov [bx], al 20023 1 C

EXECUTE mov [bx], al 20023 1 C

EXECUTE mov [bx], al 20023 1 C HIGH LOW

EXECUTE mov [bx], al 20023 1 C HIGH LOW

EXECUTE mov [bx], al 20023 1 C HIGH LOW

EXECUTE mov [bx], al 20023 1 C HIGH LOW

FETCH CS: IP

FETCH CS: IP

FETCH 1000: 0007

FETCH 1000: 0007

FETCH 10007

FETCH 10007

FETCH 10007 LOW HIGH

FETCH 10007 LOW HIGH

FETCH 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

FETCH 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

INC. PC 10007 F 4 LOW HIGH

DECODE 10007 F 4 LOW hlt HIGH

DECODE 10007 F 4 LOW hlt HIGH

EXECUTE hlt

EXECUTE hlt

8086 Instruction set summary • Data transfer operations • Arithmetic operations • Logic operation

8086 Instruction set summary • Data transfer operations • Arithmetic operations • Logic operation • Control operations • String operations • Machine control

Data Transfer Instructions • Very Common Instruction: mov desti, source • Allowed Operands Destination

Data Transfer Instructions • Very Common Instruction: mov desti, source • Allowed Operands Destination Memory Accumulator Register Memory Seg. Register Memory Source Accumulator Memory Register Immediate Register Memory Seg. Reg.

Arithmetic/Logic Instructions • Basic Mathematical Operations – Signed/Unsigned Integer Only – Default is 2’s

Arithmetic/Logic Instructions • Basic Mathematical Operations – Signed/Unsigned Integer Only – Default is 2’s Complement – Computes Result AND Modifies Status Flags • Logic Instructions – Bit Level – Word Level – Computes Results AND Modifies Status Flags

Arithmetic Instruction Summary add adc inc aaa daa sub sbb dec neg cmp das

Arithmetic Instruction Summary add adc inc aaa daa sub sbb dec neg cmp das aas mul imul aam div idiv aad ax, ax bx bx ax, ax ax ax, bx bx cx cx cl cx bx ; ax ax+bx and set flags ; ax ax+bx+CF(lsb) and set flags ; ax ax+1 and set flags ; ASCII Adjust after Addition ; Decimal (BCD) Adjust after Addition ; ax ax-bx and set flags ; ax (ax-CF)-bx and set flags ; ax ax-1 ; ax (-1)*(ax) -- 2’s Complement ; Flags are set according to ax-bx ; Decimal (BCD) Adjust after Subtraction ; ASCII Adjust after Subtraction ; dx: ax ax * cx (unsigned) ; dx: ax ax * cx (2’s complement) ; ASCII Adjust after Multiplication ; al ax/cl Quot. AND ah ax/cl Rem. ; ax (dx: ax)/cx Quot. AND dx Rem. ; ASCII Adjust after Division

Addition Instruction Types add adc inc aaa daa ax, ax Addition add al, add

Addition Instruction Types add adc inc aaa daa ax, ax Addition add al, add bx, add [bx], add cl, add al, add bx, bx bx ; ax ax+bx and set flags ; ax ax+bx+CF(lsb) and set flags ; ax ax+1 and set flags ; ASCII Adjust after Addition ; Decimal (BCD) Adjust after bl 35 afh al [bp] [ebx] TEMP[di] ; al al+bl and set flags ; bx bx+35 afh ; ds: (bx)+al ; cl cl+ss: (bp) ; al al+ds: (ebx) ; bx bx+ds: (TEMP+di)

Increment Examples inc bl ; bl bl+1 and set flags inc BYTE PTR [bx]

Increment Examples inc bl ; bl bl+1 and set flags inc BYTE PTR [bx] ; Byte at ds: (bx)+1 New MASM Directive: BYTE POINTER 00 ffh inc [bx] 00 ffh inc 0000 h [DATA 1] ; Word at ds: (bx)+1 0100 h ; ds: (DATA 1)+1

Add with Carry BX 1 1 AX DX 0 1 CX CF=1 BX CF

Add with Carry BX 1 1 AX DX 0 1 CX CF=1 BX CF add adc ax, bx, cx dx AX ; ax ax+cx and flags set ; bx bx+dx+CF(lsb) and flags set 33 -bit Sum Present in CF: bx: ax

Decimal Adjust after Addition • For BCD Arithmetic • “Corrects” Result 0110 +0111 1101

Decimal Adjust after Addition • For BCD Arithmetic • “Corrects” Result 0110 +0111 1101 6 7 13 should be 0001 0011 (1101 is illegal BCD) • 2 Digits/Word Intel Refers to as “Packed Decimal” • daa Uses Implicit Operand, al Register • Follows add, adc to “Adjust”

Decimal Adjust after Addition Example mov mov add daa mov adc daa mov dx,

Decimal Adjust after Addition Example mov mov add daa mov adc daa mov dx, bx, al, 1234 h 3099 h bl dl cl, al, al bh dh ch, al ; dx 1234 BCD ; bx 3099 BCD ; al cdh illegal BCD, need 34+99=133 ; al 33 h (33 BCD) and CF=1 ; cl 33 BCD ; al 30 h+12 h+1=43 h ; al 43 h (43 BCD) not illegal BCD this time ; cx=4333 h BCD for 1234+3099

ASCII Adjust after Addition • For Addition Using ASCII Encoded Numbers 30 h through

ASCII Adjust after Addition • For Addition Using ASCII Encoded Numbers 30 h through 39 h Represent ‘ 0’ through ‘ 9’ • ax is Default Source and Destination for aaa 31 +39 6 a ‘ 1’ ‘ 9’ ‘ 10’ should be 3130 h (6 ah is incorrect ASCII result ‘j’) mov add aaa add ax, al, ax, 31 h 39 h ; ax 0031 h=‘ 1’ ; ax 31 h+39 h=006 ah=‘<nul>j’ ; ax 0100 h (this is BCD of result) 3030 h ; Convert from BCD to ASCII ; ax 0100 h+3030 h=3130 h=‘ 10’

Subtraction Instruction Types sub sbb dec neg cmp das ax, ax ax ax, bx

Subtraction Instruction Types sub sbb dec neg cmp das ax, ax ax ax, bx bx bx ; ax ax-bx and set flags ; ax (ax-CF)-bx and set flags ; ax ax-1 ; ax (-1)*(ax) - 2’s Complement ; Flag is set according to ax-bx ; Decimal (BCD) Adjust after Subtraction ; ASCII Adjust after Subtraction

Allowable Operands for add, sub Gen Reg + - Mem Loc Immediate Destination Source

Allowable Operands for add, sub Gen Reg + - Mem Loc Immediate Destination Source Gen Reg Mem Loc + Immediate

Subtract with Borrow, sbb CF CF sub sbb ax, bx, BX AX SI DI

Subtract with Borrow, sbb CF CF sub sbb ax, bx, BX AX SI DI BX AX di si ; ax ax-di and CF gets borrow bit ; bx (bx-CF(lsb))-si and flags set 32 -bit Difference Present in bx: ax CF Indicates If Difference is Negative

Multiplication • 8086/8088 One of First to Include mul/div Instruction • Allowable Operands: Bytes,

Multiplication • 8086/8088 One of First to Include mul/div Instruction • Allowable Operands: Bytes, Words, Double. Words • Allowable Results: Words, Double. Words, Quad. Words • OF, CF Give Useful Information • AF, PF, ZF, SF Change but Contents Unpredictable • Multiplicand Always in al, ax • mul - Unsigned Mnemonic • imul - Signed Mnemonic

Multiply Instructions • Product can be Twice the Size 2 3=6 (same size) 2

Multiply Instructions • Product can be Twice the Size 2 3=6 (same size) 2 8 = 16(double size, EXT) • OF=CF=0 means product is same size as result (faster) • OF=CF=1 means EXT product size (slower) • AF, PF, ZF, SF Contents Unpredictable mul imul bl bx ; ax al*bl, Unsigned ; dx: ax bx*ax, Unsigned ; ax al*bl, Signed ; dx: ax bx*ax, Signed

Division • 8, 16, 32 bit Operands (32 bit is 386+) • No Immediate

Division • 8, 16, 32 bit Operands (32 bit is 386+) • No Immediate Addressing Mode • No Flag Bits Change Predictably • Can Cause Two Types of Error: 1) Divide by 0 (Mathematically Undefined) 2) Divide Overflow (Wordlength Problem) • Operands: Divisor is Programmer Specified • Dividend is Implied • Quotient, Remainder Implied

Division Instruction Examples • idiv Signed and div Unsigned dividend / divisor = quotient,

Division Instruction Examples • idiv Signed and div Unsigned dividend / divisor = quotient, rmdr div cx ; dx: ax is divided by value in cx ; unsigned quotient is placed in ax ; positive remainder is placed in dx idiv ebx ; edx: eax is divided by value in ebx ; signed quotient is placed in eax ; remainder (ALWAYS same sign as ; dividend) is placed in edx

Logic Instruction Types not and or xor test shl sal shr sar ax ax,

Logic Instruction Types not and or xor test shl sal shr sar ax ax, ax, BITWISE LOGICAL ; 1’s Complement-Logical Invert bx ; Bitwise logical and operation bx ; Bitwise logical inclusive-or operation bx ; Bitwise logical exclusive-or operation fffh ; Bitwise and but result discarded 4 3 SHIFT ; Logical shift left ; Arithmetic shift left ; Logical shift right ; Arithmetic shift right ROTATE rol ror rcl bx, 3 cx, 4 ax, 1 ; Rotate left ; Rotate right ; Rotate left through carry rcr dx, 6 ; Rotate right through carry

Bit Level Logic and, or, xor, not, test • Affect Status Flags as Follows:

Bit Level Logic and, or, xor, not, test • Affect Status Flags as Follows: 1) Always Clears CF and OF 2) SF, ZF, AF, PF Change to Reflect Result • Common Usage: and ax, ax ; clear CF and OF xor ax, ax ; clear ax=CF=OF=PF=AF=SF=0 and ZF=1 ; does more than mov ax, 0 h ; faster than push 00 h then popf

shl - Shifts Logical Shift Left CF shr - - - REG CF Arithmetic

shl - Shifts Logical Shift Left CF shr - - - REG CF Arithmetic Shift Left (same as logical) CF sar 0 Logical Shift Right 0 sal REG 0 Arithmetic Shift Right (sign bit is preserved) REG MSB CF

rol Rotates - Rotate Left CF rcl ror rcr REG - Rotate Through Carry

rol Rotates - Rotate Left CF rcl ror rcr REG - Rotate Through Carry Left CF REG - Rotate Right - Rotate Through Carry Right CF REG

Program Control Instructions • Generally modify CS: IP • Causes modification in execution sequence

Program Control Instructions • Generally modify CS: IP • Causes modification in execution sequence (of instructions) • When such a program flow change occurs: a) Instructions in the BIU inst. queue become invalid b) BIU directly fetches CS: IP instruction from memory c) While EU executes new instruction, BIU flushes/refills inst. queue • Classification a) Jumps - Unconditional control transfers (synchronous) b) Branches - Conditional control transfer c) Interrupts - Unconditional control transfers (asynchronous) d) Iteration - More complex type of branch

Control Instruction Summary jmp call ret hlt LABEL UNCONDITIONAL ; next instruction ; nothing

Control Instruction Summary jmp call ret hlt LABEL UNCONDITIONAL ; next instruction ; nothing executed has LABEL executed is after the call until RESET signal loop LABEL loope/loopz LABEL loopne/loopnz ITERATION ; cx - 1, jump to LABEL if cx > 0 ; same as loop but ZF=1 also required ; same as loop but ZF=0 also required into iret INTERRUPTS ; Invoke the int. handler specified by immed 8 ; same as int but OF=1 also ; Return from interrupt handler <immed 8> CONDITIONAL to follow

Simplest Control Instruction, jmp LABEL ; LABEL is offset address of instruction ; in

Simplest Control Instruction, jmp LABEL ; LABEL is offset address of instruction ; in the code segment 3 Forms of jmp SHORT - 2 bytes, allows jump to ± 127 locations from current address EB NEAR - 3 bytes, allows jump to ± 32 K locations from current address E 9 FAR disphi displo - 5 bytes anywhere in memory EA IP lo IP hi CS lo CS hi

Conditional Control Instruction Summary Simple Flag Branches Jump based on single flag CONDITIONAL jc

Conditional Control Instruction Summary Simple Flag Branches Jump based on single flag CONDITIONAL jc jnc je/jz jne/jnz jo jno js jns jp/jpe jnp/jpo LABEL LABEL LABEL ; jump ; jump ; jump on on if if if carry (CF=1) no carry (CF=0) ZF=1 - jump if equal/zero ZF=0 - jump not equal/jump if zero OF=1 - jump on overflow OF=0 - jump if no overflow sign flag set (SF=1) no sign flag (SF=0) PF=1 - jump on parity/parity even PF=0 - jump on no parity/parity odd

Conditional Control Instruction Summary Branches for unsigned comparisons Jump is based on flags used

Conditional Control Instruction Summary Branches for unsigned comparisons Jump is based on flags used for unsigned number comparison (based on C, Z flag) ja/jnbe jae/jnb jb/jnae jbe/jna LABEL ; jump Typical use: cmp al, bl jb there if if CONDITIONAL CF=ZF=0 - jump above-jump not below/equal CF=0 - jump above/equal-jump not below CF=1 - jump below-jump not above/equal CF=1 or ZF=1 - jump equal - jump zero ; jump if al is ‘below’ bl ; unsigned comparison

Conditional Control Instruction Summary Branches for signed comparisons Jump is based on flags used

Conditional Control Instruction Summary Branches for signed comparisons Jump is based on flags used for signed number comparison (based on Z, S, V flags) CONDITIONAL jg/jnle LABEL jge/jnl LABEL jl/jnge LABEL jle/jng LABEL ; jump ; Typical use: cmp al, bl jl there if ZF=0 and (SF=OF) - jump greater/not less nor equal if SF=OF - jump greater-equal/not less than if SF OF - jump less than/not greater nor equal if ZF=1 or SF OF - jump less or equal/not greater than ; jump if al is less than bl ; signed comparison

Iteration Instruction, loop • Combination of decrement cx and conditional Jump • Decrements cx

Iteration Instruction, loop • Combination of decrement cx and conditional Jump • Decrements cx and if cx 0 jumps to LABEL Example: ADDS PROC mov mov cld AGAIN: mov lodsw add mov ADDS stosw loop ret ENDP NEAR cx, si, di, bx, ax, di, AGAIN 100 ; cx 64 h - number of words to add OFFSET BLOCK 1 ; si offset of BLOCK 1 (in ds) OFFSET BLOCK 2 ; di offset of BLOCK 2 (in es) ; Auto-increment si and di, DF=0 di ; bx di, save offset of BLOCK 2 ; ax ds: [si], si si+2, di di+2 [bx] ; ax + ds: [bx] bx ; di bx, restore di with ; offset in BLOCK 2 ; es: [di] ax, si si+2, di di+2 ; cx - 1, if cx 0 jump to AGAIN ; ip ss: [sp]

Procedures • Group of instructions that perform single task – (can be used as)

Procedures • Group of instructions that perform single task – (can be used as) a SUBROUTINE call ret - invokes subroutine - pushes ip - returns from subroutine - pops ip • Must specify NEAR FAR - intrasegment - intersegment • Difference is op-code of ret NEAR FAR - c 3 h - pops IP - cbh - pops CS, pops IP

call Instruction • Differs from jmp since return address on stack NEAR call: FAR

call Instruction • Differs from jmp since return address on stack NEAR call: FAR call: 3 bytes - 1 opcode and 2 for IP 5 bytes - 1 opcode, 2 for IP and 2 for CS • call with operand - can use 16 -bit offset in any register except segment registers call bx ; pushes ip then jumps to cs: [bx]

call Instruction - Example mov call COMP PROC push mov in inc out pop

call Instruction - Example mov call COMP PROC push mov in inc out pop ret ENDP si, OFFSET COMP si. . . NEAR dx dx, 03 f 8 h al, dx dx dx, al dx

ret Instruction NEAR FAR - • • pops 16 -bit value places in IP

ret Instruction NEAR FAR - • • pops 16 -bit value places in IP pops 32 -bit value places in CS: IP Type is determined by PROC directive Other form of ret has immediate operand (8 bit) The immediate operand is added to the SP after popping the return address Example ret 6

String Transfer Instructions • String Forms: movsb movsw ; move string byte by byte

String Transfer Instructions • String Forms: movsb movsw ; move string byte by byte ; move string word by word EXAMPLE: movsb ; Copies 8 bits at DS: SI to ES: DI

Other String Instructions lodsb ; loads al with contents of ds: si ; Inc/Dec

Other String Instructions lodsb ; loads al with contents of ds: si ; Inc/Dec si by 1 depending on DF lodsw ; loads ax with ds: si ; Inc/Dec si by 2 depending on DF stosb ; loads es: di with contents of al ; Inc/Dec di by 1 depending on DF stosw ; loads es: di with contents of ax ; Inc/Dec di by 2 depending on DF

String Scan Instruction, scas • scasb, scasw • Compares al, ax • Does an

String Scan Instruction, scas • scasb, scasw • Compares al, ax • Does an integer subtraction - result not saved • Generally used with a REPEAT prefix • DF controls auto-increment/decrement • Example: mov di, cld mov cx, xor al, repne scasb OFFSET BLOCK 100 al ; di address of memory location BLOCK ; DF 0, auto-increment mode ; cx 64 h, initialize counter to 100 ; clear al ; test for 00 h in location es: di ; if es: di not equal to 00 h then ; cx - 1, di di + 1, repeat ; else if cx = 00 h ; do not repeat test ; else if es: di equals 00 h ; ZF = 1, do not repeat test

Compare String Instruction, cmps • cmpsb, cmpsw • Compares 2 sections of memory •

Compare String Instruction, cmps • cmpsb, cmpsw • Compares 2 sections of memory • Does an integer subtraction - result not saved • Generally used with a REPEAT prefix • si, di auto-increment/decrement depending on DF • Example: Test two strings for equivalence ; Assume that ds and es lea si, LINE lea di, TABLE cld moc cx, 10 repe cmpsb are already set-up (NOTE: ds can equal es) ; si gets offset of location labeled LINE ; di gets offset of location labeled TABLE ; DF=0, auto-increment mode ; initialize counter register to 10 ; while ds: si=es: di decrement cx and incr. si, di ; if cx=0 stop testing ; after complete, if cx not equal 0, then ; strings do not match

8086 Interrupts RCET Microprocessor & Microcontroller 102

8086 Interrupts RCET Microprocessor & Microcontroller 102

8086 Interrupts Procedure RCET Microprocessor & Microcontroller 103

8086 Interrupts Procedure RCET Microprocessor & Microcontroller 103

8086 External Interrupts RCET Microprocessor & Microcontroller 104

8086 External Interrupts RCET Microprocessor & Microcontroller 104

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 105

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 105

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 106

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 106

Total Memory and IVT RCET Microprocessor & Microcontroller 107

Total Memory and IVT RCET Microprocessor & Microcontroller 107